LLVMにRenesas RL78をPortingしようとしているのかな？

こんにちは。NoMaYです。

以下に投稿したBlinkyサンプルプログラムのzipファイルにリストファイル(GNURL78)と逆アセンブルダンプファイル(LLVM-RL78とGNURL78)も入れておいたのですが、内蔵周辺レジスタアクセスのコードがLLVM-RL78はGNURL78より随分悪いですね。(コンパイラでの最適化レベルは共に -Os です。) たぶんこれは、LLVM-RL78での最適化処理において抜けてしまっている何かがある、のではないだろうかと思ってしまうのです、、、

RL78/G23-64p Fast Prototyping Board Blinky sample program
japan.renesasrulz.com/cafe_rene/m/sample_program/463

●LLVM-RL78の場合

RL78_RL78G23_FPB_LLVM_e2studio/HardwareDebug/rl78g23_fpb.dmp より抜粋

0000323b _R_Config_ITL0_Create:
;     ITLCTL0 = 0x00U;
    323b: 36 66 03                      movw hl, #870
    323e: cc 00 00                      mov [hl], #0
;     ITLMKF0 |= _01_ITL_CHANNEL0_COUNT_MATCH_MASK;
    3241: 36 6c 03                      movw hl, #876
    3244: 8b                            mov a, [hl]
    3245: 71 8a                         set1 a.0
    3247: 36 6c 03                      movw hl, #876
    324a: 9b                            mov [hl], a
    324b: fd ce 32                      call !0x32ce
;     ITLMK = 1U;    /* disable INTITL interrupt */
    324e: 36 e7 ff                      movw hl, #65511
    3251: 8b                            mov a, [hl]
    3252: 71 aa                         set1 a.2
    3254: 36 e7 ff                      movw hl, #65511
    3257: 9b                            mov [hl], a
;     ITLIF = 0U;    /* clear INTITL interrupt flag */
    3258: 36 e3 ff                      movw hl, #65507
    325b: 8b                            mov a, [hl]
    325c: 71 ab                         clr1 a.2
    325e: 36 e3 ff                      movw hl, #65507
    3261: 9b                            mov [hl], a
;     ITLPR1 = 1U;
    3262: 36 ef ff                      movw hl, #65519
    3265: 8b                            mov a, [hl]
    3266: 71 aa                         set1 a.2
    3268: 36 ef ff                      movw hl, #65519
    326b: 9b                            mov [hl], a
;     ITLPR0 = 1U;
    326c: 36 eb ff                      movw hl, #65515
    326f: 8b                            mov a, [hl]
    3270: 71 aa                         set1 a.2
    3272: 36 eb ff                      movw hl, #65515
    3275: 9b                            mov [hl], a
;     ITLCTL0 |= _80_ITL_MODE_32BIT;
    3276: 36 66 03                      movw hl, #870
    3279: 8b                            mov a, [hl]
    327a: 71 fa                         set1 a.7
    327c: 36 66 03                      movw hl, #870
    327f: 9b                            mov [hl], a
;     ITLCSEL0 &= _F8_ITL_CLOCK_FITL0_CLEAR;
    3280: 36 67 03                      movw hl, #871
    3283: 51 f8                         mov a, #248
    3285: 5d                            and a, [hl]
    3286: 36 67 03                      movw hl, #871
    3289: 9b                            mov [hl], a
;     ITLCSEL0 |= _01_ITL_CLOCK_FITL0_FIHP;
    328a: 36 67 03                      movw hl, #871
    328d: 8b                            mov a, [hl]
    328e: 71 8a                         set1 a.0
    3290: 36 67 03                      movw hl, #871
    3293: 9b                            mov [hl], a
;     ITLFDIV00 &= _F8_ITL_ITL000_FITL0_CLEAR;
    3294: 36 68 03                      movw hl, #872
    3297: 51 f8                         mov a, #248
    3299: 5d                            and a, [hl]
    329a: 36 68 03                      movw hl, #872
    329d: 9b                            mov [hl], a
;     ITLFDIV00 |= _07_ITL_ITL000_FITL0_128;
    329e: 36 68 03                      movw hl, #872
    32a1: 51 07                         mov a, #7
    32a3: 6d                            or a, [hl]
    32a4: 36 68 03                      movw hl, #872
    32a7: 9b                            mov [hl], a
;     ITLCMP00 = _E847_ITL_ITLCMP00_VALUE;
    32a8: 36 60 03                      movw hl, #864
    32ab: 30 47 e8                      movw ax, #59463
    32ae: bb                            movw [hl], ax
;     ITLCMP01 = _0001_ITL_ITLCMP01_VALUE;
    32af: 36 62 03                      movw hl, #866
    32b2: e6                            onew ax
    32b3: bb                            movw [hl], ax
;     R_Config_ITL0_Create_UserInit();
    32b4: fd de 32                      call !0x32de
; }
    32b7: d7                            ret

　
●GNURL78の場合

RL78_RL78G23_FPB_GCC_e2studio/HardwareDebug/rl78g23_fpb.dmp より抜粋(＋少々加工)

00000272 <_R_Config_ITL0_Create>:
    ITLCTL0 = 0x00U;
 272:   f5 66 03                        clrb    !f0366 <__mirror_end+0xe4466>
    ITLMKF0 |= _01_ITL_CHANNEL0_COUNT_MATCH_MASK;
 275:   e4 f0                           oneb    0xffef0
 277:   8f 6c 03                        mov a, !f036c <__mirror_end+0xe446c>
 27a:   6b f0                           or  a, 0xffef0
 27c:   9f 6c 03                        mov !f036c <__mirror_end+0xe446c>, a
    ITLS0 &= (uint16_t)~_01_ITL_CHANNEL0_COUNT_MATCH_DETECTE;
 27f:   71 08 6b 03                     clr1    !f036b <__mirror_end+0xe446b>.0
    ITLMK = 1U;    /* disable INTITL interrupt */
 283:   71 2a e7                        set1    0xfffe7.2
    ITLIF = 0U;    /* clear INTITL interrupt flag */
 286:   71 2b e3                        clr1    0xfffe3.2
    ITLPR1 = 1U;
 289:   71 2a ef                        set1    0xfffef.2
    ITLPR0 = 1U;
 28c:   71 2a eb                        set1    0xfffeb.2
    ITLCTL0 |= _80_ITL_MODE_32BIT;
 28f:   71 70 66 03                     set1    !f0366 <__mirror_end+0xe4466>.7
    ITLCSEL0 &= _F8_ITL_CLOCK_FITL0_CLEAR;
 293:   8f 67 03                        mov a, !f0367 <__mirror_end+0xe4467>
 296:   5c f8                           and a, #248
 298:   9f 67 03                        mov !f0367 <__mirror_end+0xe4467>, a
    ITLCSEL0 |= _01_ITL_CLOCK_FITL0_FIHP;
 29b:   8f 67 03                        mov a, !f0367 <__mirror_end+0xe4467>
 29e:   6b f0                           or  a, 0xffef0
 2a0:   9f 67 03                        mov !f0367 <__mirror_end+0xe4467>, a
    ITLFDIV00 &= _F8_ITL_ITL000_FITL0_CLEAR;
 2a3:   8f 68 03                        mov a, !f0368 <__mirror_end+0xe4468>
 2a6:   5c f8                           and a, #248
 2a8:   9f 68 03                        mov !f0368 <__mirror_end+0xe4468>, a
    ITLFDIV00 |= _07_ITL_ITL000_FITL0_128;
 2ab:   8f 68 03                        mov a, !f0368 <__mirror_end+0xe4468>
 2ae:   6c 07                           or  a, #7
 2b0:   9f 68 03                        mov !f0368 <__mirror_end+0xe4468>, a
    ITLCMP00 = _E847_ITL_ITLCMP00_VALUE;
 2b3:   30 47 e8                        movw    ax, #0xe847
 2b6:   bf 60 03                        movw    !f0360 <__mirror_end+0xe4460>, ax
    ITLCMP01 = _0001_ITL_ITLCMP01_VALUE;
 2b9:   e6                              onew    ax
 2ba:   bf 62 03                        movw    !f0362 <__mirror_end+0xe4462>, ax
    R_Config_ITL0_Create_UserInit();
 2bd:   fd ce 02                        call    !2ce <_R_Config_ITL0_Create_UserInit>
}
 2c0:   d7                              ret

こんにちは。NoMaYです。

以下に投稿したBlinkyサンプルプログラムのzipファイルにリストファイル(GNURL78)と逆アセンブルダンプファイル(LLVM-RL78とGNURL78)も入れておいたのですが、内蔵周辺レジスタアクセスのコードがLLVM-RL78はGNURL78より随分悪いですね。(コンパイラでの最適化レベルは共に -Os です。) たぶんこれは、LLVM-RL78での最適化処理において抜けてしまっている何かがある、のではないだろうかと思ってしまうのです、、、

RL78/G23-64p Fast Prototyping Board Blinky sample program
japan.renesasrulz.com/cafe_rene/m/sample_program/463

●LLVM-RL78の場合

RL78_RL78G23_FPB_LLVM_e2studio/HardwareDebug/rl78g23_fpb.dmp より抜粋

0000323b _R_Config_ITL0_Create:
;     ITLCTL0 = 0x00U;
    323b: 36 66 03                      movw hl, #870
    323e: cc 00 00                      mov [hl], #0
;     ITLMKF0 |= _01_ITL_CHANNEL0_COUNT_MATCH_MASK;
    3241: 36 6c 03                      movw hl, #876
    3244: 8b                            mov a, [hl]
    3245: 71 8a                         set1 a.0
    3247: 36 6c 03                      movw hl, #876
    324a: 9b                            mov [hl], a
    324b: fd ce 32                      call !0x32ce
;     ITLMK = 1U;    /* disable INTITL interrupt */
    324e: 36 e7 ff                      movw hl, #65511
    3251: 8b                            mov a, [hl]
    3252: 71 aa                         set1 a.2
    3254: 36 e7 ff                      movw hl, #65511
    3257: 9b                            mov [hl], a
;     ITLIF = 0U;    /* clear INTITL interrupt flag */
    3258: 36 e3 ff                      movw hl, #65507
    325b: 8b                            mov a, [hl]
    325c: 71 ab                         clr1 a.2
    325e: 36 e3 ff                      movw hl, #65507
    3261: 9b                            mov [hl], a
;     ITLPR1 = 1U;
    3262: 36 ef ff                      movw hl, #65519
    3265: 8b                            mov a, [hl]
    3266: 71 aa                         set1 a.2
    3268: 36 ef ff                      movw hl, #65519
    326b: 9b                            mov [hl], a
;     ITLPR0 = 1U;
    326c: 36 eb ff                      movw hl, #65515
    326f: 8b                            mov a, [hl]
    3270: 71 aa                         set1 a.2
    3272: 36 eb ff                      movw hl, #65515
    3275: 9b                            mov [hl], a
;     ITLCTL0 |= _80_ITL_MODE_32BIT;
    3276: 36 66 03                      movw hl, #870
    3279: 8b                            mov a, [hl]
    327a: 71 fa                         set1 a.7
    327c: 36 66 03                      movw hl, #870
    327f: 9b                            mov [hl], a
;     ITLCSEL0 &= _F8_ITL_CLOCK_FITL0_CLEAR;
    3280: 36 67 03                      movw hl, #871
    3283: 51 f8                         mov a, #248
    3285: 5d                            and a, [hl]
    3286: 36 67 03                      movw hl, #871
    3289: 9b                            mov [hl], a
;     ITLCSEL0 |= _01_ITL_CLOCK_FITL0_FIHP;
    328a: 36 67 03                      movw hl, #871
    328d: 8b                            mov a, [hl]
    328e: 71 8a                         set1 a.0
    3290: 36 67 03                      movw hl, #871
    3293: 9b                            mov [hl], a
;     ITLFDIV00 &= _F8_ITL_ITL000_FITL0_CLEAR;
    3294: 36 68 03                      movw hl, #872
    3297: 51 f8                         mov a, #248
    3299: 5d                            and a, [hl]
    329a: 36 68 03                      movw hl, #872
    329d: 9b                            mov [hl], a
;     ITLFDIV00 |= _07_ITL_ITL000_FITL0_128;
    329e: 36 68 03                      movw hl, #872
    32a1: 51 07                         mov a, #7
    32a3: 6d                            or a, [hl]
    32a4: 36 68 03                      movw hl, #872
    32a7: 9b                            mov [hl], a
;     ITLCMP00 = _E847_ITL_ITLCMP00_VALUE;
    32a8: 36 60 03                      movw hl, #864
    32ab: 30 47 e8                      movw ax, #59463
    32ae: bb                            movw [hl], ax
;     ITLCMP01 = _0001_ITL_ITLCMP01_VALUE;
    32af: 36 62 03                      movw hl, #866
    32b2: e6                            onew ax
    32b3: bb                            movw [hl], ax
;     R_Config_ITL0_Create_UserInit();
    32b4: fd de 32                      call !0x32de
; }
    32b7: d7                            ret

　
●GNURL78の場合

RL78_RL78G23_FPB_GCC_e2studio/HardwareDebug/rl78g23_fpb.dmp より抜粋(＋少々加工)

00000272 <_R_Config_ITL0_Create>:
    ITLCTL0 = 0x00U;
 272:   f5 66 03                        clrb    !f0366 <__mirror_end+0xe4466>
    ITLMKF0 |= _01_ITL_CHANNEL0_COUNT_MATCH_MASK;
 275:   e4 f0                           oneb    0xffef0
 277:   8f 6c 03                        mov a, !f036c <__mirror_end+0xe446c>
 27a:   6b f0                           or  a, 0xffef0
 27c:   9f 6c 03                        mov !f036c <__mirror_end+0xe446c>, a
    ITLS0 &= (uint16_t)~_01_ITL_CHANNEL0_COUNT_MATCH_DETECTE;
 27f:   71 08 6b 03                     clr1    !f036b <__mirror_end+0xe446b>.0
    ITLMK = 1U;    /* disable INTITL interrupt */
 283:   71 2a e7                        set1    0xfffe7.2
    ITLIF = 0U;    /* clear INTITL interrupt flag */
 286:   71 2b e3                        clr1    0xfffe3.2
    ITLPR1 = 1U;
 289:   71 2a ef                        set1    0xfffef.2
    ITLPR0 = 1U;
 28c:   71 2a eb                        set1    0xfffeb.2
    ITLCTL0 |= _80_ITL_MODE_32BIT;
 28f:   71 70 66 03                     set1    !f0366 <__mirror_end+0xe4466>.7
    ITLCSEL0 &= _F8_ITL_CLOCK_FITL0_CLEAR;
 293:   8f 67 03                        mov a, !f0367 <__mirror_end+0xe4467>
 296:   5c f8                           and a, #248
 298:   9f 67 03                        mov !f0367 <__mirror_end+0xe4467>, a
    ITLCSEL0 |= _01_ITL_CLOCK_FITL0_FIHP;
 29b:   8f 67 03                        mov a, !f0367 <__mirror_end+0xe4467>
 29e:   6b f0                           or  a, 0xffef0
 2a0:   9f 67 03                        mov !f0367 <__mirror_end+0xe4467>, a
    ITLFDIV00 &= _F8_ITL_ITL000_FITL0_CLEAR;
 2a3:   8f 68 03                        mov a, !f0368 <__mirror_end+0xe4468>
 2a6:   5c f8                           and a, #248
 2a8:   9f 68 03                        mov !f0368 <__mirror_end+0xe4468>, a
    ITLFDIV00 |= _07_ITL_ITL000_FITL0_128;
 2ab:   8f 68 03                        mov a, !f0368 <__mirror_end+0xe4468>
 2ae:   6c 07                           or  a, #7
 2b0:   9f 68 03                        mov !f0368 <__mirror_end+0xe4468>, a
    ITLCMP00 = _E847_ITL_ITLCMP00_VALUE;
 2b3:   30 47 e8                        movw    ax, #0xe847
 2b6:   bf 60 03                        movw    !f0360 <__mirror_end+0xe4460>, ax
    ITLCMP01 = _0001_ITL_ITLCMP01_VALUE;
 2b9:   e6                              onew    ax
 2ba:   bf 62 03                        movw    !f0362 <__mirror_end+0xe4462>, ax
    R_Config_ITL0_Create_UserInit();
 2bd:   fd ce 02                        call    !2ce <_R_Config_ITL0_Create_UserInit>
}
 2c0:   d7                              ret