Project: rx64m_rsk_audio File: file:/C:/Renesas/RX/issue_20170918/workspace_e2v600/rx64m_rsk_audio/r_bsp/board/rskrx64m/resetprg.c Language: GNU C Index Version: 206.0 Build Configuration: HardwareDebug Context: file:/C:/Renesas/RX/issue_20170918/workspace_e2v600/rx64m_rsk_audio/r_bsp/board/rskrx64m/resetprg.c C, {} Versions in Index: 1 C: {}; 5 macros, 2 includes, 240 names; Include Search Path (option -I): E:\tools\micom\Renesas\CS+\CC\CC-RX\V2.03.00\\include C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_bsp C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_config C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_cmt_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_cmt_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_dmaca_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_dtc_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_ether_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_jpege_rx\lib\compress C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_jpege_rx\lib\jpege C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_pdc_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_s2_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_s2_rx\lib C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_sci_iic_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_sci_iic_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_ssi_api_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_ssi_api_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_driver_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_driver_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_file_driver_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_file_driver_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_file_driver_rx\src\use_external_mem C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_file_driver_rx\src\use_internal_mem C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_http_server_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_http_server_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_rx\lib C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_t4_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_driver_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_driver_rx\src C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_driver_rx\src\device\sdhi C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_driver_rx\src\device\usb C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_driver_rx\src\device\usb_mini C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_rx C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_tfat_rx\lib C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_usb_basic C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_usb_basic\src\driver\inc C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_usb_basic\src\HW\inc C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_usb_hmsc C:\Renesas\RX\issue_20170918\workspace_e2v600\rx64m_rsk_audio\r_usb_hmsc\src\inc Macro definitions (option -D): far= near= _far= _near= __BITRIGHT=1 __CCRX__=1 __DBL8=1 __DOFF=1 __evenaccess= __far= __FPU=1 __INTRINSIC_LIB=1 __LIT=1 __near= __RENESAS_VERSION__=0x02030000 __RENESAS__=1 __RON=1 __RX= __RX600=1 __RXV2=1 __STDC_HOSTED__=1 __STDC_VERSION__=199901L __UBIT=1 __UCHAR=1 Macro definitions (from language + headers in index): bool=_Bool brk()=_builtin_brk() BSC=(*(volatile struct st_bsc __evenaccess *)0x81300) BSP_BCLK_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_BCK_DIV) BSP_BOARD_RSKRX64M= BSP_CFG_BCK_DIV=(2) BSP_CFG_BCLK_OUTPUT=(0) BSP_CFG_BOARD_REVISION=(0) BSP_CFG_CLOCK_SOURCE=(4) BSP_CFG_FCK_DIV=(4) BSP_CFG_FILE_REVISION_MAJOR=(2) BSP_CFG_FILE_REVISION_MINOR=(80) BSP_CFG_HEAP_BYTES=(0x400) BSP_CFG_HOCO_FREQUENCY=(0) BSP_CFG_ICK_DIV=(2) BSP_CFG_IO_LIB_ENABLE=(1) BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED=(true) BSP_CFG_MCU_PART_GROUP=(0x0) BSP_CFG_MCU_PART_MEMORY_SIZE=(0x15) BSP_CFG_MCU_PART_MEMORY_TYPE=(0x0) BSP_CFG_MCU_PART_PACKAGE=(0x0) BSP_CFG_MCU_PART_SERIES=(0x0) BSP_CFG_MCU_VCC_MV=(3300) BSP_CFG_OFS0_REG_VALUE=(0xFFFFFFFF) BSP_CFG_OFS1_REG_VALUE=(0xFFFFFFFF) BSP_CFG_PARAM_CHECKING_ENABLE=(1) BSP_CFG_PCKA_DIV=(2) BSP_CFG_PCKB_DIV=(4) BSP_CFG_PCKC_DIV=(4) BSP_CFG_PCKD_DIV=(4) BSP_CFG_PLL_DIV=(1) BSP_CFG_PLL_MUL=(10.0) BSP_CFG_PLL_SRC=(0) BSP_CFG_RTOS_USED=(0) BSP_CFG_RUN_IN_USER_MODE=(0) BSP_CFG_SDCLK_OUTPUT=(0) BSP_CFG_TRUSTED_MODE_FUNCTION=(0xFFFFFFFF) BSP_CFG_UCK_DIV=(5) BSP_CFG_USER_BOOT_ENABLE=(0) BSP_CFG_USER_CHARGET_ENABLED=(0) BSP_CFG_USER_CHARGET_FUNCTION=my_sw_charget_function BSP_CFG_USER_CHARPUT_ENABLED=(0) BSP_CFG_USER_CHARPUT_FUNCTION=my_sw_charput_function BSP_CFG_USER_LOCKING_ENABLED=(0) BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION=my_hw_locking_function BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION=my_hw_unlocking_function BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION=my_sw_locking_function BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION=my_sw_unlocking_function BSP_CFG_USER_LOCKING_TYPE=bsp_lock_t BSP_CFG_USER_STACK_ENABLE=(1) BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED=(0) BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED=(0) BSP_CFG_USER_WARM_START_POST_C_FUNCTION=my_sw_warmstart_postc_function BSP_CFG_USER_WARM_START_PRE_C_FUNCTION=my_sw_warmstart_prec_function BSP_CFG_XTAL_HZ=(24000000) BSP_DATA_FLASH_SIZE_BYTES=(65536) BSP_FCLK_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) BSP_HOCO_HZ=(16000000) BSP_ICLK_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) BSP_LOCO_HZ=(240000) BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND=254 BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY=253 BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS=252 BSP_MAPPED_INT_CFG_A_VECT_GPT0_GDTE0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIA0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIB0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIC0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCID0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIE0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIF0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIU0= BSP_MAPPED_INT_CFG_A_VECT_GPT0_GTCIV0= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GDTE1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIA1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIB1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIC1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCID1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIE1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIF1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIU1= BSP_MAPPED_INT_CFG_A_VECT_GPT1_GTCIV1= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GDTE2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIA2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIB2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIC2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCID2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIE2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIF2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIU2= BSP_MAPPED_INT_CFG_A_VECT_GPT2_GTCIV2= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GDTE3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIA3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIB3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIC3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCID3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIE3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIF3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIU3= BSP_MAPPED_INT_CFG_A_VECT_GPT3_GTCIV3= BSP_MAPPED_INT_CFG_A_VECT_GPTA_ETGIN= BSP_MAPPED_INT_CFG_A_VECT_GPTA_ETGIP= BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0=209 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0=210 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0=211 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0=212 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0=214 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0=215 BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0=213 BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1=208 BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1=216 BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1=218 BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1=217 BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2=219 BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2=220 BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2=222 BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2=221 BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3=223 BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3=224 BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3=225 BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3=226 BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3=227 BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4=228 BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4=229 BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4=230 BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4=231 BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4=232 BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5=233 BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5=234 BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5=235 BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6=236 BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6=237 BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6=238 BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6=239 BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6=240 BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7=241 BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7=242 BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7=243 BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7=244 BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7=245 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8=246 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8=247 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8=248 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8=249 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8=251 BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8=250 BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0=177 BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0=179 BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0=178 BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0=180 BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1=181 BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1=183 BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1=182 BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1=184 BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2=185 BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2=187 BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2=186 BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2=188 BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2=128 BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3=129 BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0=168 BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0=169 BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0=170 BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0=171 BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1=172 BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1=173 BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1=174 BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1=175 BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND=194 BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I=198 BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I=199 BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND=197 BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP=176 BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0=190 BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0=191 BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1=192 BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1=193 BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND=195 BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND=196 BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0=146 BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0=147 BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0=148 BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1=149 BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1=150 BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1=151 BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2=152 BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2=153 BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2=154 BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3=155 BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3=156 BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3=157 BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A=130 BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B=131 BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C=132 BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D=133 BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V=134 BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A=144 BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B=135 BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U=137 BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V=136 BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A=138 BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B=139 BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U=141 BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V=140 BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A=142 BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B=143 BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C=145 BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D=158 BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V=159 BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A=160 BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B=161 BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U=163 BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V=162 BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A=164 BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B=165 BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U=167 BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V=166 BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0=189 BSP_MCU_IPL_MAX=(0xF) BSP_MCU_IPL_MIN=(0) BSP_MCU_RX64M=(1) BSP_MCU_RX64_ALL=(1) BSP_MCU_SERIES_RX600=(1) BSP_PACKAGE_LQFP176=(1) BSP_PACKAGE_PINS=(176) BSP_PCLKA_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV) BSP_PCLKB_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) BSP_PCLKC_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV) BSP_PCLKD_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) BSP_PRIV_CALC_IER_REG(x)=(((x - BSP_PRV_B_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START) BSP_PRV_A=A BSP_PRV_A_INT_VECTOR_END=(255) BSP_PRV_A_INT_VECTOR_START=(208) BSP_PRV_B=B BSP_PRV_B_INT_VECTOR_END=(207) BSP_PRV_B_INT_VECTOR_START=(128) BSP_PRV_CALC_128_MOD_8=0 BSP_PRV_CALC_129_MOD_8=1 BSP_PRV_CALC_130_MOD_8=2 BSP_PRV_CALC_131_MOD_8=3 BSP_PRV_CALC_132_MOD_8=4 BSP_PRV_CALC_133_MOD_8=5 BSP_PRV_CALC_134_MOD_8=6 BSP_PRV_CALC_135_MOD_8=7 BSP_PRV_CALC_136_MOD_8=0 BSP_PRV_CALC_137_MOD_8=1 BSP_PRV_CALC_138_MOD_8=2 BSP_PRV_CALC_139_MOD_8=3 BSP_PRV_CALC_140_MOD_8=4 BSP_PRV_CALC_141_MOD_8=5 BSP_PRV_CALC_142_MOD_8=6 BSP_PRV_CALC_143_MOD_8=7 BSP_PRV_CALC_144_MOD_8=0 BSP_PRV_CALC_145_MOD_8=1 BSP_PRV_CALC_146_MOD_8=2 BSP_PRV_CALC_147_MOD_8=3 BSP_PRV_CALC_148_MOD_8=4 BSP_PRV_CALC_149_MOD_8=5 BSP_PRV_CALC_150_MOD_8=6 BSP_PRV_CALC_151_MOD_8=7 BSP_PRV_CALC_152_MOD_8=0 BSP_PRV_CALC_153_MOD_8=1 BSP_PRV_CALC_154_MOD_8=2 BSP_PRV_CALC_155_MOD_8=3 BSP_PRV_CALC_156_MOD_8=4 BSP_PRV_CALC_157_MOD_8=5 BSP_PRV_CALC_158_MOD_8=6 BSP_PRV_CALC_159_MOD_8=7 BSP_PRV_CALC_160_MOD_8=0 BSP_PRV_CALC_161_MOD_8=1 BSP_PRV_CALC_162_MOD_8=2 BSP_PRV_CALC_163_MOD_8=3 BSP_PRV_CALC_164_MOD_8=4 BSP_PRV_CALC_165_MOD_8=5 BSP_PRV_CALC_166_MOD_8=6 BSP_PRV_CALC_167_MOD_8=7 BSP_PRV_CALC_168_MOD_8=0 BSP_PRV_CALC_169_MOD_8=1 BSP_PRV_CALC_170_MOD_8=2 BSP_PRV_CALC_171_MOD_8=3 BSP_PRV_CALC_172_MOD_8=4 BSP_PRV_CALC_173_MOD_8=5 BSP_PRV_CALC_174_MOD_8=6 BSP_PRV_CALC_175_MOD_8=7 BSP_PRV_CALC_176_MOD_8=0 BSP_PRV_CALC_177_MOD_8=1 BSP_PRV_CALC_178_MOD_8=2 BSP_PRV_CALC_179_MOD_8=3 BSP_PRV_CALC_180_MOD_8=4 BSP_PRV_CALC_181_MOD_8=5 BSP_PRV_CALC_182_MOD_8=6 BSP_PRV_CALC_183_MOD_8=7 BSP_PRV_CALC_184_MOD_8=0 BSP_PRV_CALC_185_MOD_8=1 BSP_PRV_CALC_186_MOD_8=2 BSP_PRV_CALC_187_MOD_8=3 BSP_PRV_CALC_188_MOD_8=4 BSP_PRV_CALC_189_MOD_8=5 BSP_PRV_CALC_190_MOD_8=6 BSP_PRV_CALC_191_MOD_8=7 BSP_PRV_CALC_192_MOD_8=0 BSP_PRV_CALC_193_MOD_8=1 BSP_PRV_CALC_194_MOD_8=2 BSP_PRV_CALC_195_MOD_8=3 BSP_PRV_CALC_196_MOD_8=4 BSP_PRV_CALC_197_MOD_8=5 BSP_PRV_CALC_198_MOD_8=6 BSP_PRV_CALC_199_MOD_8=7 BSP_PRV_CALC_200_MOD_8=0 BSP_PRV_CALC_201_MOD_8=1 BSP_PRV_CALC_202_MOD_8=2 BSP_PRV_CALC_203_MOD_8=3 BSP_PRV_CALC_204_MOD_8=4 BSP_PRV_CALC_205_MOD_8=5 BSP_PRV_CALC_206_MOD_8=6 BSP_PRV_CALC_207_MOD_8=7 BSP_PRV_CALC_208_MOD_8=0 BSP_PRV_CALC_209_MOD_8=1 BSP_PRV_CALC_210_MOD_8=2 BSP_PRV_CALC_211_MOD_8=3 BSP_PRV_CALC_212_MOD_8=4 BSP_PRV_CALC_213_MOD_8=5 BSP_PRV_CALC_214_MOD_8=6 BSP_PRV_CALC_215_MOD_8=7 BSP_PRV_CALC_216_MOD_8=0 BSP_PRV_CALC_217_MOD_8=1 BSP_PRV_CALC_218_MOD_8=2 BSP_PRV_CALC_219_MOD_8=3 BSP_PRV_CALC_220_MOD_8=4 BSP_PRV_CALC_221_MOD_8=5 BSP_PRV_CALC_222_MOD_8=6 BSP_PRV_CALC_223_MOD_8=7 BSP_PRV_CALC_224_MOD_8=0 BSP_PRV_CALC_225_MOD_8=1 BSP_PRV_CALC_226_MOD_8=2 BSP_PRV_CALC_227_MOD_8=3 BSP_PRV_CALC_228_MOD_8=4 BSP_PRV_CALC_229_MOD_8=5 BSP_PRV_CALC_230_MOD_8=6 BSP_PRV_CALC_231_MOD_8=7 BSP_PRV_CALC_232_MOD_8=0 BSP_PRV_CALC_233_MOD_8=1 BSP_PRV_CALC_234_MOD_8=2 BSP_PRV_CALC_235_MOD_8=3 BSP_PRV_CALC_236_MOD_8=4 BSP_PRV_CALC_237_MOD_8=5 BSP_PRV_CALC_238_MOD_8=6 BSP_PRV_CALC_239_MOD_8=7 BSP_PRV_CALC_240_MOD_8=0 BSP_PRV_CALC_241_MOD_8=1 BSP_PRV_CALC_242_MOD_8=2 BSP_PRV_CALC_243_MOD_8=3 BSP_PRV_CALC_244_MOD_8=4 BSP_PRV_CALC_245_MOD_8=5 BSP_PRV_CALC_246_MOD_8=6 BSP_PRV_CALC_247_MOD_8=7 BSP_PRV_CALC_248_MOD_8=0 BSP_PRV_CALC_249_MOD_8=1 BSP_PRV_CALC_250_MOD_8=2 BSP_PRV_CALC_251_MOD_8=3 BSP_PRV_CALC_252_MOD_8=4 BSP_PRV_CALC_253_MOD_8=5 BSP_PRV_CALC_254_MOD_8=6 BSP_PRV_CALC_255_MOD_8=7 BSP_PRV_DTCE(x,y)=_BSP_PRV_DTCE(x, y) BSP_PRV_IEN(x)=_BSP_PRV_IEN(x) BSP_PRV_INT_A_NUM_AES_AESEND=89 BSP_PRV_INT_A_NUM_AES_AESRDY=88 BSP_PRV_INT_A_NUM_EPTPC_IPLS=86 BSP_PRV_INT_A_NUM_GPT0_GDTE0=51 BSP_PRV_INT_A_NUM_GPT0_GTCIA0=47 BSP_PRV_INT_A_NUM_GPT0_GTCIB0=48 BSP_PRV_INT_A_NUM_GPT0_GTCIC0=49 BSP_PRV_INT_A_NUM_GPT0_GTCID0=50 BSP_PRV_INT_A_NUM_GPT0_GTCIE0=52 BSP_PRV_INT_A_NUM_GPT0_GTCIF0=53 BSP_PRV_INT_A_NUM_GPT0_GTCIU0=55 BSP_PRV_INT_A_NUM_GPT0_GTCIV0=54 BSP_PRV_INT_A_NUM_GPT1_GDTE1=62 BSP_PRV_INT_A_NUM_GPT1_GTCIA1=58 BSP_PRV_INT_A_NUM_GPT1_GTCIB1=59 BSP_PRV_INT_A_NUM_GPT1_GTCIC1=60 BSP_PRV_INT_A_NUM_GPT1_GTCID1=61 BSP_PRV_INT_A_NUM_GPT1_GTCIE1=63 BSP_PRV_INT_A_NUM_GPT1_GTCIF1=64 BSP_PRV_INT_A_NUM_GPT1_GTCIU1=66 BSP_PRV_INT_A_NUM_GPT1_GTCIV1=65 BSP_PRV_INT_A_NUM_GPT2_GDTE2=71 BSP_PRV_INT_A_NUM_GPT2_GTCIA2=67 BSP_PRV_INT_A_NUM_GPT2_GTCIB2=68 BSP_PRV_INT_A_NUM_GPT2_GTCIC2=69 BSP_PRV_INT_A_NUM_GPT2_GTCID2=70 BSP_PRV_INT_A_NUM_GPT2_GTCIE2=72 BSP_PRV_INT_A_NUM_GPT2_GTCIF2=73 BSP_PRV_INT_A_NUM_GPT2_GTCIU2=75 BSP_PRV_INT_A_NUM_GPT2_GTCIV2=74 BSP_PRV_INT_A_NUM_GPT3_GDTE3=80 BSP_PRV_INT_A_NUM_GPT3_GTCIA3=76 BSP_PRV_INT_A_NUM_GPT3_GTCIB3=77 BSP_PRV_INT_A_NUM_GPT3_GTCIC3=78 BSP_PRV_INT_A_NUM_GPT3_GTCID3=79 BSP_PRV_INT_A_NUM_GPT3_GTCIE3=81 BSP_PRV_INT_A_NUM_GPT3_GTCIF3=82 BSP_PRV_INT_A_NUM_GPT3_GTCIU3=84 BSP_PRV_INT_A_NUM_GPT3_GTCIV3=83 BSP_PRV_INT_A_NUM_GPTA_ETGIN=56 BSP_PRV_INT_A_NUM_GPTA_ETGIP=57 BSP_PRV_INT_A_NUM_MTU0_TGIA0=1 BSP_PRV_INT_A_NUM_MTU0_TGIB0=2 BSP_PRV_INT_A_NUM_MTU0_TGIC0=3 BSP_PRV_INT_A_NUM_MTU0_TGID0=4 BSP_PRV_INT_A_NUM_MTU0_TGIE0=6 BSP_PRV_INT_A_NUM_MTU0_TGIF0=7 BSP_PRV_INT_A_NUM_MTU0_TGIV0=5 BSP_PRV_INT_A_NUM_MTU1_TGIA1=8 BSP_PRV_INT_A_NUM_MTU1_TGIB1=9 BSP_PRV_INT_A_NUM_MTU1_TGIU1=11 BSP_PRV_INT_A_NUM_MTU1_TGIV1=10 BSP_PRV_INT_A_NUM_MTU2_TGIA2=12 BSP_PRV_INT_A_NUM_MTU2_TGIB2=13 BSP_PRV_INT_A_NUM_MTU2_TGIU2=15 BSP_PRV_INT_A_NUM_MTU2_TGIV2=14 BSP_PRV_INT_A_NUM_MTU3_TGIA3=16 BSP_PRV_INT_A_NUM_MTU3_TGIB3=17 BSP_PRV_INT_A_NUM_MTU3_TGIC3=18 BSP_PRV_INT_A_NUM_MTU3_TGID3=19 BSP_PRV_INT_A_NUM_MTU3_TGIV3=20 BSP_PRV_INT_A_NUM_MTU4_TGIA4=21 BSP_PRV_INT_A_NUM_MTU4_TGIB4=22 BSP_PRV_INT_A_NUM_MTU4_TGIC4=23 BSP_PRV_INT_A_NUM_MTU4_TGID4=24 BSP_PRV_INT_A_NUM_MTU4_TGIV4=25 BSP_PRV_INT_A_NUM_MTU5_TGIU5=27 BSP_PRV_INT_A_NUM_MTU5_TGIV5=28 BSP_PRV_INT_A_NUM_MTU5_TGIW5=29 BSP_PRV_INT_A_NUM_MTU6_TGIA6=30 BSP_PRV_INT_A_NUM_MTU6_TGIB6=31 BSP_PRV_INT_A_NUM_MTU6_TGIC6=32 BSP_PRV_INT_A_NUM_MTU6_TGID6=33 BSP_PRV_INT_A_NUM_MTU6_TGIV6=34 BSP_PRV_INT_A_NUM_MTU7_TGIA7=35 BSP_PRV_INT_A_NUM_MTU7_TGIB7=36 BSP_PRV_INT_A_NUM_MTU7_TGIC7=37 BSP_PRV_INT_A_NUM_MTU7_TGID7=38 BSP_PRV_INT_A_NUM_MTU7_TGIV7=39 BSP_PRV_INT_A_NUM_MTU8_TGIA8=41 BSP_PRV_INT_A_NUM_MTU8_TGIB8=42 BSP_PRV_INT_A_NUM_MTU8_TGIC8=43 BSP_PRV_INT_A_NUM_MTU8_TGID8=44 BSP_PRV_INT_A_NUM_MTU8_TGIU8=46 BSP_PRV_INT_A_NUM_MTU8_TGIV8=45 BSP_PRV_INT_A_SELECT_208=ICU.SLIAR208.BYTE BSP_PRV_INT_A_SELECT_209=ICU.SLIAR209.BYTE BSP_PRV_INT_A_SELECT_210=ICU.SLIAR210.BYTE BSP_PRV_INT_A_SELECT_211=ICU.SLIAR211.BYTE BSP_PRV_INT_A_SELECT_212=ICU.SLIAR212.BYTE BSP_PRV_INT_A_SELECT_213=ICU.SLIAR213.BYTE BSP_PRV_INT_A_SELECT_214=ICU.SLIAR214.BYTE BSP_PRV_INT_A_SELECT_215=ICU.SLIAR215.BYTE BSP_PRV_INT_A_SELECT_216=ICU.SLIAR216.BYTE BSP_PRV_INT_A_SELECT_217=ICU.SLIAR217.BYTE BSP_PRV_INT_A_SELECT_218=ICU.SLIAR218.BYTE BSP_PRV_INT_A_SELECT_219=ICU.SLIAR219.BYTE BSP_PRV_INT_A_SELECT_220=ICU.SLIAR220.BYTE BSP_PRV_INT_A_SELECT_221=ICU.SLIAR221.BYTE BSP_PRV_INT_A_SELECT_222=ICU.SLIAR222.BYTE BSP_PRV_INT_A_SELECT_223=ICU.SLIAR223.BYTE BSP_PRV_INT_A_SELECT_224=ICU.SLIAR224.BYTE BSP_PRV_INT_A_SELECT_225=ICU.SLIAR225.BYTE BSP_PRV_INT_A_SELECT_226=ICU.SLIAR226.BYTE BSP_PRV_INT_A_SELECT_227=ICU.SLIAR227.BYTE BSP_PRV_INT_A_SELECT_228=ICU.SLIAR228.BYTE BSP_PRV_INT_A_SELECT_229=ICU.SLIAR229.BYTE BSP_PRV_INT_A_SELECT_230=ICU.SLIAR230.BYTE BSP_PRV_INT_A_SELECT_231=ICU.SLIAR231.BYTE BSP_PRV_INT_A_SELECT_232=ICU.SLIAR232.BYTE BSP_PRV_INT_A_SELECT_233=ICU.SLIAR233.BYTE BSP_PRV_INT_A_SELECT_234=ICU.SLIAR234.BYTE BSP_PRV_INT_A_SELECT_235=ICU.SLIAR235.BYTE BSP_PRV_INT_A_SELECT_236=ICU.SLIAR236.BYTE BSP_PRV_INT_A_SELECT_237=ICU.SLIAR237.BYTE BSP_PRV_INT_A_SELECT_238=ICU.SLIAR238.BYTE BSP_PRV_INT_A_SELECT_239=ICU.SLIAR239.BYTE BSP_PRV_INT_A_SELECT_240=ICU.SLIAR240.BYTE BSP_PRV_INT_A_SELECT_241=ICU.SLIAR241.BYTE BSP_PRV_INT_A_SELECT_242=ICU.SLIAR242.BYTE BSP_PRV_INT_A_SELECT_243=ICU.SLIAR243.BYTE BSP_PRV_INT_A_SELECT_244=ICU.SLIAR244.BYTE BSP_PRV_INT_A_SELECT_245=ICU.SLIAR245.BYTE BSP_PRV_INT_A_SELECT_246=ICU.SLIAR246.BYTE BSP_PRV_INT_A_SELECT_247=ICU.SLIAR247.BYTE BSP_PRV_INT_A_SELECT_248=ICU.SLIAR248.BYTE BSP_PRV_INT_A_SELECT_249=ICU.SLIAR249.BYTE BSP_PRV_INT_A_SELECT_250=ICU.SLIAR250.BYTE BSP_PRV_INT_A_SELECT_251=ICU.SLIAR251.BYTE BSP_PRV_INT_A_SELECT_252=ICU.SLIAR252.BYTE BSP_PRV_INT_A_SELECT_253=ICU.SLIAR253.BYTE BSP_PRV_INT_A_SELECT_254=ICU.SLIAR254.BYTE BSP_PRV_INT_A_SELECT_255=ICU.SLIAR255.BYTE BSP_PRV_INT_B_NUM_CAN0_RXF0=50 BSP_PRV_INT_B_NUM_CAN0_RXM0=52 BSP_PRV_INT_B_NUM_CAN0_TXF0=51 BSP_PRV_INT_B_NUM_CAN0_TXM0=53 BSP_PRV_INT_B_NUM_CAN1_RXF1=54 BSP_PRV_INT_B_NUM_CAN1_RXM1=56 BSP_PRV_INT_B_NUM_CAN1_TXF1=55 BSP_PRV_INT_B_NUM_CAN1_TXM1=57 BSP_PRV_INT_B_NUM_CAN2_RXF2=58 BSP_PRV_INT_B_NUM_CAN2_RXM2=60 BSP_PRV_INT_B_NUM_CAN2_TXF2=59 BSP_PRV_INT_B_NUM_CAN2_TXM2=61 BSP_PRV_INT_B_NUM_CMT2_CMI2=1 BSP_PRV_INT_B_NUM_CMT3_CMI3=2 BSP_PRV_INT_B_NUM_CMTW0_IC0I0=41 BSP_PRV_INT_B_NUM_CMTW0_IC1I0=42 BSP_PRV_INT_B_NUM_CMTW0_OC0I0=43 BSP_PRV_INT_B_NUM_CMTW0_OC1I0=44 BSP_PRV_INT_B_NUM_CMTW1_IC0I1=45 BSP_PRV_INT_B_NUM_CMTW1_IC1I1=46 BSP_PRV_INT_B_NUM_CMTW1_OC0I1=47 BSP_PRV_INT_B_NUM_CMTW1_OC1I1=48 BSP_PRV_INT_B_NUM_DES_DESEND=73 BSP_PRV_INT_B_NUM_ELC_ELSR18I=79 BSP_PRV_INT_B_NUM_ELC_ELSR19I=80 BSP_PRV_INT_B_NUM_RNG_RNGEND=76 BSP_PRV_INT_B_NUM_RTC_CUP=49 BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0=64 BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0=65 BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1=68 BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1=69 BSP_PRV_INT_B_NUM_SHA_SHADEND=74 BSP_PRV_INT_B_NUM_SHA_SHAEND=75 BSP_PRV_INT_B_NUM_TMR0_CMIA0=3 BSP_PRV_INT_B_NUM_TMR0_CMIB0=4 BSP_PRV_INT_B_NUM_TMR0_OVI0=5 BSP_PRV_INT_B_NUM_TMR1_CMIA1=6 BSP_PRV_INT_B_NUM_TMR1_CMIB1=7 BSP_PRV_INT_B_NUM_TMR1_OVI1=8 BSP_PRV_INT_B_NUM_TMR2_CMIA2=9 BSP_PRV_INT_B_NUM_TMR2_CMIB2=10 BSP_PRV_INT_B_NUM_TMR2_OVI2=11 BSP_PRV_INT_B_NUM_TMR3_CMIA3=12 BSP_PRV_INT_B_NUM_TMR3_CMIB3=13 BSP_PRV_INT_B_NUM_TMR3_OVI3=14 BSP_PRV_INT_B_NUM_TPU0_TGI0A=15 BSP_PRV_INT_B_NUM_TPU0_TGI0B=16 BSP_PRV_INT_B_NUM_TPU0_TGI0C=17 BSP_PRV_INT_B_NUM_TPU0_TGI0D=18 BSP_PRV_INT_B_NUM_TPU0_TGI0V=19 BSP_PRV_INT_B_NUM_TPU1_TGI1A=20 BSP_PRV_INT_B_NUM_TPU1_TGI1B=21 BSP_PRV_INT_B_NUM_TPU1_TGI1U=23 BSP_PRV_INT_B_NUM_TPU1_TGI1V=22 BSP_PRV_INT_B_NUM_TPU2_TGI2A=24 BSP_PRV_INT_B_NUM_TPU2_TGI2B=25 BSP_PRV_INT_B_NUM_TPU2_TGI2U=27 BSP_PRV_INT_B_NUM_TPU2_TGI2V=26 BSP_PRV_INT_B_NUM_TPU3_TGI3A=28 BSP_PRV_INT_B_NUM_TPU3_TGI3B=29 BSP_PRV_INT_B_NUM_TPU3_TGI3C=30 BSP_PRV_INT_B_NUM_TPU3_TGI3D=31 BSP_PRV_INT_B_NUM_TPU3_TGI3V=32 BSP_PRV_INT_B_NUM_TPU4_TGI4A=33 BSP_PRV_INT_B_NUM_TPU4_TGI4B=34 BSP_PRV_INT_B_NUM_TPU4_TGI4U=36 BSP_PRV_INT_B_NUM_TPU4_TGI4V=35 BSP_PRV_INT_B_NUM_TPU5_TGI5A=37 BSP_PRV_INT_B_NUM_TPU5_TGI5B=38 BSP_PRV_INT_B_NUM_TPU5_TGI5U=40 BSP_PRV_INT_B_NUM_TPU5_TGI5V=39 BSP_PRV_INT_B_NUM_USB0_USBI0=62 BSP_PRV_INT_B_SELECT_128=ICU.SLIBXR128.BYTE BSP_PRV_INT_B_SELECT_129=ICU.SLIBXR129.BYTE BSP_PRV_INT_B_SELECT_130=ICU.SLIBXR130.BYTE BSP_PRV_INT_B_SELECT_131=ICU.SLIBXR131.BYTE BSP_PRV_INT_B_SELECT_132=ICU.SLIBXR132.BYTE BSP_PRV_INT_B_SELECT_133=ICU.SLIBXR133.BYTE BSP_PRV_INT_B_SELECT_134=ICU.SLIBXR134.BYTE BSP_PRV_INT_B_SELECT_135=ICU.SLIBXR135.BYTE BSP_PRV_INT_B_SELECT_136=ICU.SLIBXR136.BYTE BSP_PRV_INT_B_SELECT_137=ICU.SLIBXR137.BYTE BSP_PRV_INT_B_SELECT_138=ICU.SLIBXR138.BYTE BSP_PRV_INT_B_SELECT_139=ICU.SLIBXR139.BYTE BSP_PRV_INT_B_SELECT_140=ICU.SLIBXR140.BYTE BSP_PRV_INT_B_SELECT_141=ICU.SLIBXR141.BYTE BSP_PRV_INT_B_SELECT_142=ICU.SLIBXR142.BYTE BSP_PRV_INT_B_SELECT_143=ICU.SLIBXR143.BYTE BSP_PRV_INT_B_SELECT_144=ICU.SLIBR144.BYTE BSP_PRV_INT_B_SELECT_145=ICU.SLIBR145.BYTE BSP_PRV_INT_B_SELECT_146=ICU.SLIBR146.BYTE BSP_PRV_INT_B_SELECT_147=ICU.SLIBR147.BYTE BSP_PRV_INT_B_SELECT_148=ICU.SLIBR148.BYTE BSP_PRV_INT_B_SELECT_149=ICU.SLIBR149.BYTE BSP_PRV_INT_B_SELECT_150=ICU.SLIBR150.BYTE BSP_PRV_INT_B_SELECT_151=ICU.SLIBR151.BYTE BSP_PRV_INT_B_SELECT_152=ICU.SLIBR152.BYTE BSP_PRV_INT_B_SELECT_153=ICU.SLIBR153.BYTE BSP_PRV_INT_B_SELECT_154=ICU.SLIBR154.BYTE BSP_PRV_INT_B_SELECT_155=ICU.SLIBR155.BYTE BSP_PRV_INT_B_SELECT_156=ICU.SLIBR156.BYTE BSP_PRV_INT_B_SELECT_157=ICU.SLIBR157.BYTE BSP_PRV_INT_B_SELECT_158=ICU.SLIBR158.BYTE BSP_PRV_INT_B_SELECT_159=ICU.SLIBR159.BYTE BSP_PRV_INT_B_SELECT_160=ICU.SLIBR160.BYTE BSP_PRV_INT_B_SELECT_161=ICU.SLIBR161.BYTE BSP_PRV_INT_B_SELECT_162=ICU.SLIBR162.BYTE BSP_PRV_INT_B_SELECT_163=ICU.SLIBR163.BYTE BSP_PRV_INT_B_SELECT_164=ICU.SLIBR164.BYTE BSP_PRV_INT_B_SELECT_165=ICU.SLIBR165.BYTE BSP_PRV_INT_B_SELECT_166=ICU.SLIBR166.BYTE BSP_PRV_INT_B_SELECT_167=ICU.SLIBR167.BYTE BSP_PRV_INT_B_SELECT_168=ICU.SLIBR168.BYTE BSP_PRV_INT_B_SELECT_169=ICU.SLIBR169.BYTE BSP_PRV_INT_B_SELECT_170=ICU.SLIBR170.BYTE BSP_PRV_INT_B_SELECT_171=ICU.SLIBR171.BYTE BSP_PRV_INT_B_SELECT_172=ICU.SLIBR172.BYTE BSP_PRV_INT_B_SELECT_173=ICU.SLIBR173.BYTE BSP_PRV_INT_B_SELECT_174=ICU.SLIBR174.BYTE BSP_PRV_INT_B_SELECT_175=ICU.SLIBR175.BYTE BSP_PRV_INT_B_SELECT_176=ICU.SLIBR176.BYTE BSP_PRV_INT_B_SELECT_177=ICU.SLIBR177.BYTE BSP_PRV_INT_B_SELECT_178=ICU.SLIBR178.BYTE BSP_PRV_INT_B_SELECT_179=ICU.SLIBR179.BYTE BSP_PRV_INT_B_SELECT_180=ICU.SLIBR180.BYTE BSP_PRV_INT_B_SELECT_181=ICU.SLIBR181.BYTE BSP_PRV_INT_B_SELECT_182=ICU.SLIBR182.BYTE BSP_PRV_INT_B_SELECT_183=ICU.SLIBR183.BYTE BSP_PRV_INT_B_SELECT_184=ICU.SLIBR184.BYTE BSP_PRV_INT_B_SELECT_185=ICU.SLIBR185.BYTE BSP_PRV_INT_B_SELECT_186=ICU.SLIBR186.BYTE BSP_PRV_INT_B_SELECT_187=ICU.SLIBR187.BYTE BSP_PRV_INT_B_SELECT_188=ICU.SLIBR188.BYTE BSP_PRV_INT_B_SELECT_189=ICU.SLIBR189.BYTE BSP_PRV_INT_B_SELECT_190=ICU.SLIBR190.BYTE BSP_PRV_INT_B_SELECT_191=ICU.SLIBR191.BYTE BSP_PRV_INT_B_SELECT_192=ICU.SLIBR192.BYTE BSP_PRV_INT_B_SELECT_193=ICU.SLIBR193.BYTE BSP_PRV_INT_B_SELECT_194=ICU.SLIBR194.BYTE BSP_PRV_INT_B_SELECT_195=ICU.SLIBR195.BYTE BSP_PRV_INT_B_SELECT_196=ICU.SLIBR196.BYTE BSP_PRV_INT_B_SELECT_197=ICU.SLIBR197.BYTE BSP_PRV_INT_B_SELECT_198=ICU.SLIBR198.BYTE BSP_PRV_INT_B_SELECT_199=ICU.SLIBR199.BYTE BSP_PRV_INT_B_SELECT_200=ICU.SLIBR200.BYTE BSP_PRV_INT_B_SELECT_201=ICU.SLIBR201.BYTE BSP_PRV_INT_B_SELECT_202=ICU.SLIBR202.BYTE BSP_PRV_INT_B_SELECT_203=ICU.SLIBR203.BYTE BSP_PRV_INT_B_SELECT_204=ICU.SLIBR204.BYTE BSP_PRV_INT_B_SELECT_205=ICU.SLIBR205.BYTE BSP_PRV_INT_B_SELECT_206=ICU.SLIBR206.BYTE BSP_PRV_INT_B_SELECT_207=ICU.SLIBR207.BYTE BSP_PRV_INT_SELECT(x,y)=_BSP_PRV_INT_SELECT(x, y) BSP_PRV_IPR(x,y)=_BSP_PRV_IPR(x, y) BSP_PRV_IR(x,y)=_BSP_PRV_IR(x, y) BSP_PRV_MAP_INT_IER_START=(0x10) BSP_PRV_SLIBR_END=(207) BSP_PRV_SLIBR_START=(144) BSP_PRV_SLIBXR_END=(143) BSP_PRV_SLIBXR_START=(128) BSP_PRV_VALID_MAP_INT(x,y)=(((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END)) BSP_PRV_VECT(x,y)=_BSP_PRV_VECT(x, y) BSP_RAM_SIZE_BYTES=(524288) BSP_ROM_SIZE_BYTES=(4194304) BSP_SELECTED_CLOCK_HZ=((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) BSP_SUB_CLOCK_HZ=(32768) BSP_UCLK_HZ=(BSP_SELECTED_CLOCK_HZ / BSP_CFG_UCK_DIV) CAC=(*(volatile struct st_cac __evenaccess *)0x8B000) CAN0=(*(volatile struct st_can __evenaccess *)0x90200) CAN1=(*(volatile struct st_can __evenaccess *)0x91200) CAN2=(*(volatile struct st_can __evenaccess *)0x92200) chg_pmusr()=_builtin_chg_pmusr() CLR(x,y)=_CLR( _ ## x ## _ ## y ) clrpsw_i()=_builtin_clrpsw_i() CLR_CAN0_ERS0=CLR0 CLR_CAN1_ERS1=CLR1 CLR_CAN2_ERS2=CLR2 CMT0=(*(volatile struct st_cmt0 __evenaccess *)0x88002) CMT1=(*(volatile struct st_cmt0 __evenaccess *)0x88008) CMT2=(*(volatile struct st_cmt0 __evenaccess *)0x88012) CMT3=(*(volatile struct st_cmt0 __evenaccess *)0x88018) CMT=(*(volatile struct st_cmt __evenaccess *)0x88000) CMTW0=(*(volatile struct st_cmtw __evenaccess *)0x94200) CMTW1=(*(volatile struct st_cmtw __evenaccess *)0x94280) CRC=(*(volatile struct st_crc __evenaccess *)0x88280) DA=(*(volatile struct st_da __evenaccess *)0x88040) DMAC0=(*(volatile struct st_dmac0 __evenaccess *)0x82000) DMAC1=(*(volatile struct st_dmac1 __evenaccess *)0x82040) DMAC2=(*(volatile struct st_dmac1 __evenaccess *)0x82080) DMAC3=(*(volatile struct st_dmac1 __evenaccess *)0x820C0) DMAC4=(*(volatile struct st_dmac1 __evenaccess *)0x82100) DMAC5=(*(volatile struct st_dmac1 __evenaccess *)0x82140) DMAC6=(*(volatile struct st_dmac1 __evenaccess *)0x82180) DMAC7=(*(volatile struct st_dmac1 __evenaccess *)0x821C0) DMAC=(*(volatile struct st_dmac __evenaccess *)0x82200) DOC=(*(volatile struct st_doc __evenaccess *)0x8B080) DTC=(*(volatile struct st_dtc __evenaccess *)0x82400) DTCE(x,y)=_DTCE( _ ## x ## _ ## y ) DTCE_AES_AESEND=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) DTCE_AES_AESRDY=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) DTCE_CAN0_RXF0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) DTCE_CAN0_RXM0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) DTCE_CAN0_TXF0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) DTCE_CAN0_TXM0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) DTCE_CAN1_RXF1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) DTCE_CAN1_RXM1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) DTCE_CAN1_TXF1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) DTCE_CAN1_TXM1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) DTCE_CAN2_RXF2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) DTCE_CAN2_RXM2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) DTCE_CAN2_TXF2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) DTCE_CAN2_TXM2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) DTCE_CMT2_CMI2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) DTCE_CMT3_CMI3=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) DTCE_CMTW0_IC0I0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) DTCE_CMTW0_IC1I0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) DTCE_CMTW0_OC0I0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) DTCE_CMTW0_OC1I0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) DTCE_CMTW1_IC0I1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) DTCE_CMTW1_IC1I1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) DTCE_CMTW1_OC0I1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) DTCE_CMTW1_OC1I1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) DTCE_DES_DESEND=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) DTCE_ELC_ELSR18I=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) DTCE_ELC_ELSR19I=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) DTCE_EPTPC_IPLS=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) DTCE_MTU0_TGIA0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) DTCE_MTU0_TGIB0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) DTCE_MTU0_TGIC0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) DTCE_MTU0_TGID0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) DTCE_MTU0_TGIE0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) DTCE_MTU0_TGIF0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) DTCE_MTU0_TGIV0=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) DTCE_MTU1_TGIA1=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) DTCE_MTU1_TGIB1=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) DTCE_MTU1_TGIU1=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) DTCE_MTU1_TGIV1=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) DTCE_MTU2_TGIA2=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) DTCE_MTU2_TGIB2=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) DTCE_MTU2_TGIU2=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) DTCE_MTU2_TGIV2=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) DTCE_MTU3_TGIA3=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) DTCE_MTU3_TGIB3=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) DTCE_MTU3_TGIC3=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) DTCE_MTU3_TGID3=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) DTCE_MTU3_TGIV3=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) DTCE_MTU4_TGIA4=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) DTCE_MTU4_TGIB4=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) DTCE_MTU4_TGIC4=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) DTCE_MTU4_TGID4=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) DTCE_MTU4_TGIV4=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) DTCE_MTU5_TGIU5=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) DTCE_MTU5_TGIV5=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) DTCE_MTU5_TGIW5=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) DTCE_MTU6_TGIA6=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) DTCE_MTU6_TGIB6=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) DTCE_MTU6_TGIC6=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) DTCE_MTU6_TGID6=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) DTCE_MTU6_TGIV6=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) DTCE_MTU7_TGIA7=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) DTCE_MTU7_TGIB7=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) DTCE_MTU7_TGIC7=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) DTCE_MTU7_TGID7=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) DTCE_MTU7_TGIV7=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) DTCE_MTU8_TGIA8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) DTCE_MTU8_TGIB8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) DTCE_MTU8_TGIC8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) DTCE_MTU8_TGID8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) DTCE_MTU8_TGIU8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) DTCE_MTU8_TGIV8=BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) DTCE_RNG_RNGEND=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) DTCE_RTC_CUP=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) DTCE_S12ADC0_S12ADI0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) DTCE_S12ADC0_S12GBADI0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) DTCE_S12ADC1_S12ADI1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) DTCE_S12ADC1_S12GBADI1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) DTCE_SHA_SHADEND=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) DTCE_SHA_SHAEND=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) DTCE_TMR0_CMIA0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) DTCE_TMR0_CMIB0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) DTCE_TMR0_OVI0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) DTCE_TMR1_CMIA1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) DTCE_TMR1_CMIB1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) DTCE_TMR1_OVI1=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) DTCE_TMR2_CMIA2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) DTCE_TMR2_CMIB2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) DTCE_TMR2_OVI2=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) DTCE_TMR3_CMIA3=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) DTCE_TMR3_CMIB3=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) DTCE_TMR3_OVI3=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) DTCE_TPU0_TGI0A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) DTCE_TPU0_TGI0B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) DTCE_TPU0_TGI0C=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) DTCE_TPU0_TGI0D=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) DTCE_TPU0_TGI0V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) DTCE_TPU1_TGI1A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) DTCE_TPU1_TGI1B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) DTCE_TPU1_TGI1U=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) DTCE_TPU1_TGI1V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) DTCE_TPU2_TGI2A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) DTCE_TPU2_TGI2B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) DTCE_TPU2_TGI2U=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) DTCE_TPU2_TGI2V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) DTCE_TPU3_TGI3A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) DTCE_TPU3_TGI3B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) DTCE_TPU3_TGI3C=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) DTCE_TPU3_TGI3D=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) DTCE_TPU3_TGI3V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) DTCE_TPU4_TGI4A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) DTCE_TPU4_TGI4B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) DTCE_TPU4_TGI4U=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) DTCE_TPU4_TGI4V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) DTCE_TPU5_TGI5A=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) DTCE_TPU5_TGI5B=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) DTCE_TPU5_TGI5U=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) DTCE_TPU5_TGI5V=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) DTCE_USB0_USBI0=BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) E2BIG=0x0007 EACCES=0x000D EAGAIN=0x000B EBADF=0x0009 EBADMSG=0x004D EBUSY=0x0010 ECANCELED=0x002F ECBASE=0x04B0 ECCRAM=(*(volatile struct st_eccram __evenaccess *)0x812C0) ECHILD=0x000A EDBLO=0x04E2 EDBLU=0x04EC EDEADLK=0x002D EDMAC0=(*(volatile struct st_edmac __evenaccess *)0xC0000) EDMAC1=(*(volatile struct st_edmac __evenaccess *)0xC0200) EDOM=0x0021 EEXIST=0x0011 EEXP=0x04B4 EEXPN=0x04B6 EFAULT=0x000E EFBIG=0x001B EFLOATO=0x04BA EFLOATU=0x04C4 EFLSFRSM=2121 EFLSRESM=2120 EFPOS=0x0098 EFPSWFRSM=2141 EFPSWRESM=2140 EILSEQ=0x0058 EINPROGRESS=0x0096 EINTR=0x0004 EINVAL=0x0016 EIO=0x0005 EISDIR=0x0015 ELC=(*(volatile struct st_elc __evenaccess *)0x8B100) ELDBLO=0x04F6 ELDBLU=0x0500 EMALFRSM=2101 EMALRESM=2100 EMBLNFRSM=2131 EMBLNRESM=2130 EMFILE=0x0018 EMLINK=0x001F EMSGSIZE=0x0061 emul(data1,data2)=_builtin_emul(data1, data2) emulu(data1,data2)=_builtin_emulu(data1, data2) EN(x,y)=_EN( _ ## x ## _ ## y ) ENAMETOOLONG=0x004E ENFILE=0x0017 ENODEV=0x0013 ENOENT=0x0002 ENOEXEC=0x0008 ENOLCK=0x002E ENOMEM=0x000C ENOSPC=0x001C ENOSYS=0x0059 ENOTDIR=0x0014 ENOTEMPTY=0x005D ENOTSUP=0x0030 ENOTTY=0x0019 ENXIO=0x0006 EN_CAC_FERRF=EN26 EN_CAC_MENDF=EN27 EN_CAC_OVFF=EN28 EN_CAN0_ERS0=EN0 EN_CAN1_ERS1=EN1 EN_CAN2_ERS2=EN2 EN_DOC_DOPCF=EN29 EN_EDMAC0_EINT0=EN4 EN_EDMAC1_EINT1=EN5 EN_EPTPC_MINT=EN0 EN_MMCIF_ACCIO=EN8 EN_MMCIF_CDETIO=EN6 EN_MMCIF_ERRIO=EN7 EN_PDC_PCERI=EN31 EN_PDC_PCFEI=EN30 EN_POE3_OEI1=EN9 EN_POE3_OEI2=EN10 EN_POE3_OEI3=EN11 EN_POE3_OEI4=EN12 EN_PRPEDMAC_PINT=EN1 EN_QSPI_QSPSSLI=EN24 EN_RIIC0_EEI0=EN14 EN_RIIC0_TEI0=EN13 EN_RIIC2_EEI2=EN16 EN_RIIC2_TEI2=EN15 EN_RSPI0_SPEI0=EN17 EN_RSPI0_SPII0=EN16 EN_S12AD0_S12CMPI0=EN20 EN_S12AD1_S12CMPI1=EN22 EN_SCI0_ERI0=EN1 EN_SCI0_TEI0=EN0 EN_SCI12_ERI12=EN17 EN_SCI12_SCIX0=EN18 EN_SCI12_SCIX1=EN19 EN_SCI12_SCIX2=EN20 EN_SCI12_SCIX3=EN21 EN_SCI12_TEI12=EN16 EN_SCI1_ERI1=EN3 EN_SCI1_TEI1=EN2 EN_SCI2_ERI2=EN5 EN_SCI2_TEI2=EN4 EN_SCI3_ERI3=EN7 EN_SCI3_TEI3=EN6 EN_SCI4_ERI4=EN9 EN_SCI4_TEI4=EN8 EN_SCI5_ERI5=EN11 EN_SCI5_TEI5=EN10 EN_SCI6_ERI6=EN13 EN_SCI6_TEI6=EN12 EN_SCI7_ERI7=EN15 EN_SCI7_TEI7=EN14 EN_SCIFA10_BRIF10=EN10 EN_SCIFA10_DRIF10=EN11 EN_SCIFA10_ERIF10=EN9 EN_SCIFA10_TEIF10=EN8 EN_SCIFA11_BRIF11=EN14 EN_SCIFA11_DRIF11=EN15 EN_SCIFA11_ERIF11=EN13 EN_SCIFA11_TEIF11=EN12 EN_SCIFA8_BRIF8=EN2 EN_SCIFA8_DRIF8=EN3 EN_SCIFA8_ERIF8=EN1 EN_SCIFA8_TEIF8=EN0 EN_SCIFA9_BRIF9=EN6 EN_SCIFA9_DRIF9=EN7 EN_SCIFA9_ERIF9=EN5 EN_SCIFA9_TEIF9=EN4 EN_SDHI_CACI=EN4 EN_SDHI_CDETI=EN3 EN_SDHI_SDACI=EN5 EN_SRC_CEF=EN2 EN_SRC_OVF=EN1 EN_SRC_PCERI=EN0 EN_SSI0_SSIF0=EN17 EN_SSI1_SSIF1=EN18 EPERM=0x0001 EPIPE=0x0020 EPTPC0=(*(volatile struct st_eptpc0 __evenaccess *)0xC4800) EPTPC1=(*(volatile struct st_eptpc0 __evenaccess *)0xC4C00) EPTPC=(*(volatile struct st_eptpc __evenaccess *)0xC0500) ERANGE=0x0022 EROFS=0x001E errno=_errno ESPIPE=0x001D ESRCH=0x0003 ESTRN=0x0450 ETHERC0=(*(volatile struct st_etherc __evenaccess *)0xC0100) ETHERC1=(*(volatile struct st_etherc __evenaccess *)0xC0300) ETIMEDOUT=0x0091 ETLN=0x04B2 ETOKFRSM=2111 ETOKRESM=2110 EXDEV=0x0012 EXDMAC0=(*(volatile struct st_exdmac0 __evenaccess *)0x82800) EXDMAC1=(*(volatile struct st_exdmac1 __evenaccess *)0x82840) EXDMAC=(*(volatile struct st_exdmac __evenaccess *)0x82A00) false=0 FIT_NO_FUNC=((void (*)(void *))0x10000000) FIT_NO_PTR=((void *)0x10000000) FLASH=(*(volatile struct st_flash __evenaccess *)0x8C294) GCR_CAN0_ERS0=GCRBE0 GCR_CAN1_ERS1=GCRBE0 GCR_CAN2_ERS2=GCRBE0 GEN_CAC_FERRF=GENBL0 GEN_CAC_MENDF=GENBL0 GEN_CAC_OVFF=GENBL0 GEN_CAN0_ERS0=GENBE0 GEN_CAN1_ERS1=GENBE0 GEN_CAN2_ERS2=GENBE0 GEN_DOC_DOPCF=GENBL0 GEN_EDMAC0_EINT0=GENAL1 GEN_EDMAC1_EINT1=GENAL1 GEN_EPTPC_MINT=GENAL1 GEN_MMCIF_ACCIO=GENBL1 GEN_MMCIF_CDETIO=GENBL1 GEN_MMCIF_ERRIO=GENBL1 GEN_PDC_PCERI=GENBL0 GEN_PDC_PCFEI=GENBL0 GEN_POE3_OEI1=GENBL1 GEN_POE3_OEI2=GENBL1 GEN_POE3_OEI3=GENBL1 GEN_POE3_OEI4=GENBL1 GEN_PRPEDMAC_PINT=GENAL1 GEN_QSPI_QSPSSLI=GENBL0 GEN_RIIC0_EEI0=GENBL1 GEN_RIIC0_TEI0=GENBL1 GEN_RIIC2_EEI2=GENBL1 GEN_RIIC2_TEI2=GENBL1 GEN_RSPI0_SPEI0=GENAL0 GEN_RSPI0_SPII0=GENAL0 GEN_S12AD0_S12CMPI0=GENBL1 GEN_S12AD1_S12CMPI1=GENBL1 GEN_SCI0_ERI0=GENBL0 GEN_SCI0_TEI0=GENBL0 GEN_SCI12_ERI12=GENBL0 GEN_SCI12_SCIX0=GENBL0 GEN_SCI12_SCIX1=GENBL0 GEN_SCI12_SCIX2=GENBL0 GEN_SCI12_SCIX3=GENBL0 GEN_SCI12_TEI12=GENBL0 GEN_SCI1_ERI1=GENBL0 GEN_SCI1_TEI1=GENBL0 GEN_SCI2_ERI2=GENBL0 GEN_SCI2_TEI2=GENBL0 GEN_SCI3_ERI3=GENBL0 GEN_SCI3_TEI3=GENBL0 GEN_SCI4_ERI4=GENBL0 GEN_SCI4_TEI4=GENBL0 GEN_SCI5_ERI5=GENBL0 GEN_SCI5_TEI5=GENBL0 GEN_SCI6_ERI6=GENBL0 GEN_SCI6_TEI6=GENBL0 GEN_SCI7_ERI7=GENBL0 GEN_SCI7_TEI7=GENBL0 GEN_SCIFA10_BRIF10=GENAL0 GEN_SCIFA10_DRIF10=GENAL0 GEN_SCIFA10_ERIF10=GENAL0 GEN_SCIFA10_TEIF10=GENAL0 GEN_SCIFA11_BRIF11=GENAL0 GEN_SCIFA11_DRIF11=GENAL0 GEN_SCIFA11_ERIF11=GENAL0 GEN_SCIFA11_TEIF11=GENAL0 GEN_SCIFA8_BRIF8=GENAL0 GEN_SCIFA8_DRIF8=GENAL0 GEN_SCIFA8_ERIF8=GENAL0 GEN_SCIFA8_TEIF8=GENAL0 GEN_SCIFA9_BRIF9=GENAL0 GEN_SCIFA9_DRIF9=GENAL0 GEN_SCIFA9_ERIF9=GENAL0 GEN_SCIFA9_TEIF9=GENAL0 GEN_SDHI_CACI=GENBL1 GEN_SDHI_CDETI=GENBL1 GEN_SDHI_SDACI=GENBL1 GEN_SRC_CEF=GENBL1 GEN_SRC_OVF=GENBL1 GEN_SRC_PCERI=GENBL1 GEN_SSI0_SSIF0=GENBL1 GEN_SSI1_SSIF1=GENBL1 get_acc()=_builtin_get_acc() get_bpc()=_builtin_get_bpc() get_bpsw()=_builtin_get_bpsw() get_extb()=_builtin_get_extb() get_fintv()=_builtin_get_fintv() get_fpsw()=_builtin_get_fpsw() get_intb()=_builtin_get_intb() get_ipl()=_builtin_get_ipl() get_isp()=_builtin_get_isp() get_psw()=_builtin_get_psw() get_usp()=_builtin_get_usp() GPT0=(*(volatile struct st_gpt0 __evenaccess *)0xC2100) GPT1=(*(volatile struct st_gpt0 __evenaccess *)0xC2180) GPT2=(*(volatile struct st_gpt0 __evenaccess *)0xC2200) GPT3=(*(volatile struct st_gpt0 __evenaccess *)0xC2280) GPT=(*(volatile struct st_gpt __evenaccess *)0xC2000) GRP_CAC_FERRF=GRPBL0 GRP_CAC_MENDF=GRPBL0 GRP_CAC_OVFF=GRPBL0 GRP_CAN0_ERS0=GRPBE0 GRP_CAN1_ERS1=GRPBE0 GRP_CAN2_ERS2=GRPBE0 GRP_DOC_DOPCF=GRPBL0 GRP_EDMAC0_EINT0=GRPAL1 GRP_EDMAC1_EINT1=GRPAL1 GRP_EPTPC_MINT=GRPAL1 GRP_MMCIF_ACCIO=GRPBL1 GRP_MMCIF_CDETIO=GRPBL1 GRP_MMCIF_ERRIO=GRPBL1 GRP_PDC_PCERI=GRPBL0 GRP_PDC_PCFEI=GRPBL0 GRP_POE3_OEI1=GRPBL1 GRP_POE3_OEI2=GRPBL1 GRP_POE3_OEI3=GRPBL1 GRP_POE3_OEI4=GRPBL1 GRP_PRPEDMAC_PINT=GRPAL1 GRP_QSPI_QSPSSLI=GRPBL0 GRP_RIIC0_EEI0=GRPBL1 GRP_RIIC0_TEI0=GRPBL1 GRP_RIIC2_EEI2=GRPBL1 GRP_RIIC2_TEI2=GRPBL1 GRP_RSPI0_SPEI0=GRPAL0 GRP_RSPI0_SPII0=GRPAL0 GRP_S12AD0_S12CMPI0=GRPBL1 GRP_S12AD1_S12CMPI1=GRPBL1 GRP_SCI0_ERI0=GRPBL0 GRP_SCI0_TEI0=GRPBL0 GRP_SCI12_ERI12=GRPBL0 GRP_SCI12_SCIX0=GRPBL0 GRP_SCI12_SCIX1=GRPBL0 GRP_SCI12_SCIX2=GRPBL0 GRP_SCI12_SCIX3=GRPBL0 GRP_SCI12_TEI12=GRPBL0 GRP_SCI1_ERI1=GRPBL0 GRP_SCI1_TEI1=GRPBL0 GRP_SCI2_ERI2=GRPBL0 GRP_SCI2_TEI2=GRPBL0 GRP_SCI3_ERI3=GRPBL0 GRP_SCI3_TEI3=GRPBL0 GRP_SCI4_ERI4=GRPBL0 GRP_SCI4_TEI4=GRPBL0 GRP_SCI5_ERI5=GRPBL0 GRP_SCI5_TEI5=GRPBL0 GRP_SCI6_ERI6=GRPBL0 GRP_SCI6_TEI6=GRPBL0 GRP_SCI7_ERI7=GRPBL0 GRP_SCI7_TEI7=GRPBL0 GRP_SCIFA10_BRIF10=GRPAL0 GRP_SCIFA10_DRIF10=GRPAL0 GRP_SCIFA10_ERIF10=GRPAL0 GRP_SCIFA10_TEIF10=GRPAL0 GRP_SCIFA11_BRIF11=GRPAL0 GRP_SCIFA11_DRIF11=GRPAL0 GRP_SCIFA11_ERIF11=GRPAL0 GRP_SCIFA11_TEIF11=GRPAL0 GRP_SCIFA8_BRIF8=GRPAL0 GRP_SCIFA8_DRIF8=GRPAL0 GRP_SCIFA8_ERIF8=GRPAL0 GRP_SCIFA8_TEIF8=GRPAL0 GRP_SCIFA9_BRIF9=GRPAL0 GRP_SCIFA9_DRIF9=GRPAL0 GRP_SCIFA9_ERIF9=GRPAL0 GRP_SCIFA9_TEIF9=GRPAL0 GRP_SDHI_CACI=GRPBL1 GRP_SDHI_CDETI=GRPBL1 GRP_SDHI_SDACI=GRPBL1 GRP_SRC_CEF=GRPBL1 GRP_SRC_OVF=GRPBL1 GRP_SRC_PCERI=GRPBL1 GRP_SSI0_SSIF0=GRPBL1 GRP_SSI1_SSIF1=GRPBL1 HWSETUP_H= ICU=(*(volatile struct st_icu __evenaccess *)0x87000) IEN(x,y)=_IEN( _ ## x ## _ ## y ) IEN_AES_AESEND=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) IEN_AES_AESRDY=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) IEN_BSC_BUSERR=IEN0 IEN_CAN0_RXF0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) IEN_CAN0_RXM0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) IEN_CAN0_TXF0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) IEN_CAN0_TXM0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) IEN_CAN1_RXF1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) IEN_CAN1_RXM1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) IEN_CAN1_TXF1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) IEN_CAN1_TXM1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) IEN_CAN2_RXF2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) IEN_CAN2_RXM2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) IEN_CAN2_TXF2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) IEN_CAN2_TXM2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) IEN_CMT0_CMI0=IEN4 IEN_CMT1_CMI1=IEN5 IEN_CMT2_CMI2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) IEN_CMT3_CMI3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) IEN_CMTW0_CMWI0=IEN6 IEN_CMTW0_IC0I0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) IEN_CMTW0_IC1I0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) IEN_CMTW0_OC0I0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) IEN_CMTW0_OC1I0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) IEN_CMTW1_CMWI1=IEN7 IEN_CMTW1_IC0I1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) IEN_CMTW1_IC1I1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) IEN_CMTW1_OC0I1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) IEN_CMTW1_OC1I1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) IEN_DES_DESEND=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) IEN_DMAC_DMAC0I=IEN0 IEN_DMAC_DMAC1I=IEN1 IEN_DMAC_DMAC2I=IEN2 IEN_DMAC_DMAC3I=IEN3 IEN_DMAC_DMAC74I=IEN4 IEN_ELC_ELSR18I=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) IEN_ELC_ELSR19I=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) IEN_EPTPC_IPLS=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) IEN_EXDMAC_EXDMAC0I=IEN6 IEN_EXDMAC_EXDMAC1I=IEN7 IEN_FCU_FIFERR=IEN5 IEN_FCU_FRDYI=IEN7 IEN_ICU_GROUPAL0=IEN0 IEN_ICU_GROUPAL1=IEN1 IEN_ICU_GROUPBE0=IEN2 IEN_ICU_GROUPBL0=IEN6 IEN_ICU_GROUPBL1=IEN7 IEN_ICU_IRQ0=IEN0 IEN_ICU_IRQ10=IEN2 IEN_ICU_IRQ11=IEN3 IEN_ICU_IRQ12=IEN4 IEN_ICU_IRQ13=IEN5 IEN_ICU_IRQ14=IEN6 IEN_ICU_IRQ15=IEN7 IEN_ICU_IRQ1=IEN1 IEN_ICU_IRQ2=IEN2 IEN_ICU_IRQ3=IEN3 IEN_ICU_IRQ4=IEN4 IEN_ICU_IRQ5=IEN5 IEN_ICU_IRQ6=IEN6 IEN_ICU_IRQ7=IEN7 IEN_ICU_IRQ8=IEN0 IEN_ICU_IRQ9=IEN1 IEN_ICU_SWINT2=IEN2 IEN_ICU_SWINT=IEN3 IEN_IWDT_IWUNI=IEN7 IEN_LVD1_LVD1=IEN0 IEN_LVD2_LVD2=IEN1 IEN_MMCIF_MBFAI=IEN5 IEN_MTU0_TGIA0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) IEN_MTU0_TGIB0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) IEN_MTU0_TGIC0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) IEN_MTU0_TGID0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) IEN_MTU0_TGIE0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) IEN_MTU0_TGIF0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) IEN_MTU0_TGIV0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) IEN_MTU1_TGIA1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) IEN_MTU1_TGIB1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) IEN_MTU1_TGIU1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) IEN_MTU1_TGIV1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) IEN_MTU2_TGIA2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) IEN_MTU2_TGIB2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) IEN_MTU2_TGIU2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) IEN_MTU2_TGIV2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) IEN_MTU3_TGIA3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) IEN_MTU3_TGIB3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) IEN_MTU3_TGIC3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) IEN_MTU3_TGID3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) IEN_MTU3_TGIV3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) IEN_MTU4_TGIA4=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) IEN_MTU4_TGIB4=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) IEN_MTU4_TGIC4=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) IEN_MTU4_TGID4=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) IEN_MTU4_TGIV4=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) IEN_MTU5_TGIU5=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) IEN_MTU5_TGIV5=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) IEN_MTU5_TGIW5=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) IEN_MTU6_TGIA6=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) IEN_MTU6_TGIB6=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) IEN_MTU6_TGIC6=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) IEN_MTU6_TGID6=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) IEN_MTU6_TGIV6=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) IEN_MTU7_TGIA7=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) IEN_MTU7_TGIB7=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) IEN_MTU7_TGIC7=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) IEN_MTU7_TGID7=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) IEN_MTU7_TGIV7=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) IEN_MTU8_TGIA8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) IEN_MTU8_TGIB8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) IEN_MTU8_TGIC8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) IEN_MTU8_TGID8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) IEN_MTU8_TGIU8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) IEN_MTU8_TGIV8=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) IEN_OST_OST=IEN5 IEN_PDC_PCDFI=IEN1 IEN_PERIA_INTA208=IEN0 IEN_PERIA_INTA209=IEN1 IEN_PERIA_INTA210=IEN2 IEN_PERIA_INTA211=IEN3 IEN_PERIA_INTA212=IEN4 IEN_PERIA_INTA213=IEN5 IEN_PERIA_INTA214=IEN6 IEN_PERIA_INTA215=IEN7 IEN_PERIA_INTA216=IEN0 IEN_PERIA_INTA217=IEN1 IEN_PERIA_INTA218=IEN2 IEN_PERIA_INTA219=IEN3 IEN_PERIA_INTA220=IEN4 IEN_PERIA_INTA221=IEN5 IEN_PERIA_INTA222=IEN6 IEN_PERIA_INTA223=IEN7 IEN_PERIA_INTA224=IEN0 IEN_PERIA_INTA225=IEN1 IEN_PERIA_INTA226=IEN2 IEN_PERIA_INTA227=IEN3 IEN_PERIA_INTA228=IEN4 IEN_PERIA_INTA229=IEN5 IEN_PERIA_INTA230=IEN6 IEN_PERIA_INTA231=IEN7 IEN_PERIA_INTA232=IEN0 IEN_PERIA_INTA233=IEN1 IEN_PERIA_INTA234=IEN2 IEN_PERIA_INTA235=IEN3 IEN_PERIA_INTA236=IEN4 IEN_PERIA_INTA237=IEN5 IEN_PERIA_INTA238=IEN6 IEN_PERIA_INTA239=IEN7 IEN_PERIA_INTA240=IEN0 IEN_PERIA_INTA241=IEN1 IEN_PERIA_INTA242=IEN2 IEN_PERIA_INTA243=IEN3 IEN_PERIA_INTA244=IEN4 IEN_PERIA_INTA245=IEN5 IEN_PERIA_INTA246=IEN6 IEN_PERIA_INTA247=IEN7 IEN_PERIA_INTA248=IEN0 IEN_PERIA_INTA249=IEN1 IEN_PERIA_INTA250=IEN2 IEN_PERIA_INTA251=IEN3 IEN_PERIA_INTA252=IEN4 IEN_PERIA_INTA253=IEN5 IEN_PERIA_INTA254=IEN6 IEN_PERIA_INTA255=IEN7 IEN_PERIB_INTB128=IEN0 IEN_PERIB_INTB129=IEN1 IEN_PERIB_INTB130=IEN2 IEN_PERIB_INTB131=IEN3 IEN_PERIB_INTB132=IEN4 IEN_PERIB_INTB133=IEN5 IEN_PERIB_INTB134=IEN6 IEN_PERIB_INTB135=IEN7 IEN_PERIB_INTB136=IEN0 IEN_PERIB_INTB137=IEN1 IEN_PERIB_INTB138=IEN2 IEN_PERIB_INTB139=IEN3 IEN_PERIB_INTB140=IEN4 IEN_PERIB_INTB141=IEN5 IEN_PERIB_INTB142=IEN6 IEN_PERIB_INTB143=IEN7 IEN_PERIB_INTB144=IEN0 IEN_PERIB_INTB145=IEN1 IEN_PERIB_INTB146=IEN2 IEN_PERIB_INTB147=IEN3 IEN_PERIB_INTB148=IEN4 IEN_PERIB_INTB149=IEN5 IEN_PERIB_INTB150=IEN6 IEN_PERIB_INTB151=IEN7 IEN_PERIB_INTB152=IEN0 IEN_PERIB_INTB153=IEN1 IEN_PERIB_INTB154=IEN2 IEN_PERIB_INTB155=IEN3 IEN_PERIB_INTB156=IEN4 IEN_PERIB_INTB157=IEN5 IEN_PERIB_INTB158=IEN6 IEN_PERIB_INTB159=IEN7 IEN_PERIB_INTB160=IEN0 IEN_PERIB_INTB161=IEN1 IEN_PERIB_INTB162=IEN2 IEN_PERIB_INTB163=IEN3 IEN_PERIB_INTB164=IEN4 IEN_PERIB_INTB165=IEN5 IEN_PERIB_INTB166=IEN6 IEN_PERIB_INTB167=IEN7 IEN_PERIB_INTB168=IEN0 IEN_PERIB_INTB169=IEN1 IEN_PERIB_INTB170=IEN2 IEN_PERIB_INTB171=IEN3 IEN_PERIB_INTB172=IEN4 IEN_PERIB_INTB173=IEN5 IEN_PERIB_INTB174=IEN6 IEN_PERIB_INTB175=IEN7 IEN_PERIB_INTB176=IEN0 IEN_PERIB_INTB177=IEN1 IEN_PERIB_INTB178=IEN2 IEN_PERIB_INTB179=IEN3 IEN_PERIB_INTB180=IEN4 IEN_PERIB_INTB181=IEN5 IEN_PERIB_INTB182=IEN6 IEN_PERIB_INTB183=IEN7 IEN_PERIB_INTB184=IEN0 IEN_PERIB_INTB185=IEN1 IEN_PERIB_INTB186=IEN2 IEN_PERIB_INTB187=IEN3 IEN_PERIB_INTB188=IEN4 IEN_PERIB_INTB189=IEN5 IEN_PERIB_INTB190=IEN6 IEN_PERIB_INTB191=IEN7 IEN_PERIB_INTB192=IEN0 IEN_PERIB_INTB193=IEN1 IEN_PERIB_INTB194=IEN2 IEN_PERIB_INTB195=IEN3 IEN_PERIB_INTB196=IEN4 IEN_PERIB_INTB197=IEN5 IEN_PERIB_INTB198=IEN6 IEN_PERIB_INTB199=IEN7 IEN_PERIB_INTB200=IEN0 IEN_PERIB_INTB201=IEN1 IEN_PERIB_INTB202=IEN2 IEN_PERIB_INTB203=IEN3 IEN_PERIB_INTB204=IEN4 IEN_PERIB_INTB205=IEN5 IEN_PERIB_INTB206=IEN6 IEN_PERIB_INTB207=IEN7 IEN_QSPI_SPRI=IEN2 IEN_QSPI_SPTI=IEN3 IEN_RAM_RAMERR=IEN2 IEN_RIIC0_RXI0=IEN4 IEN_RIIC0_TXI0=IEN5 IEN_RIIC2_RXI2=IEN6 IEN_RIIC2_TXI2=IEN7 IEN_RNG_RNGEND=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) IEN_RSPI0_SPRI0=IEN6 IEN_RSPI0_SPTI0=IEN7 IEN_RTC_ALM=IEN4 IEN_RTC_CUP=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) IEN_RTC_PRD=IEN5 IEN_S12ADC0_S12ADI0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) IEN_S12ADC0_S12GBADI0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) IEN_S12ADC1_S12ADI1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) IEN_S12ADC1_S12GBADI1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) IEN_SCI0_RXI0=IEN2 IEN_SCI0_TXI0=IEN3 IEN_SCI12_RXI12=IEN4 IEN_SCI12_TXI12=IEN5 IEN_SCI1_RXI1=IEN4 IEN_SCI1_TXI1=IEN5 IEN_SCI2_RXI2=IEN6 IEN_SCI2_TXI2=IEN7 IEN_SCI3_RXI3=IEN0 IEN_SCI3_TXI3=IEN1 IEN_SCI4_RXI4=IEN2 IEN_SCI4_TXI4=IEN3 IEN_SCI5_RXI5=IEN4 IEN_SCI5_TXI5=IEN5 IEN_SCI6_RXI6=IEN6 IEN_SCI6_TXI6=IEN7 IEN_SCI7_RXI7=IEN2 IEN_SCI7_TXI7=IEN3 IEN_SCIFA10_RXIF10=IEN0 IEN_SCIFA10_TXIF10=IEN1 IEN_SCIFA11_RXIF11=IEN2 IEN_SCIFA11_TXIF11=IEN3 IEN_SCIFA8_RXIF8=IEN4 IEN_SCIFA8_TXIF8=IEN5 IEN_SCIFA9_RXIF9=IEN6 IEN_SCIFA9_TXIF9=IEN7 IEN_SDHI_SBFAI=IEN4 IEN_SHA_SHADEND=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) IEN_SHA_SHAEND=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) IEN_SRC_IDEI=IEN2 IEN_SRC_ODFI=IEN3 IEN_SSI0_SSIRXI0=IEN7 IEN_SSI0_SSITXI0=IEN6 IEN_SSI1_SSIRTI1=IEN0 IEN_TMR0_CMIA0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) IEN_TMR0_CMIB0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) IEN_TMR0_OVI0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) IEN_TMR1_CMIA1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) IEN_TMR1_CMIB1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) IEN_TMR1_OVI1=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) IEN_TMR2_CMIA2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) IEN_TMR2_CMIB2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) IEN_TMR2_OVI2=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) IEN_TMR3_CMIA3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) IEN_TMR3_CMIB3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) IEN_TMR3_OVI3=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) IEN_TPU0_TGI0A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) IEN_TPU0_TGI0B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) IEN_TPU0_TGI0C=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) IEN_TPU0_TGI0D=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) IEN_TPU0_TGI0V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) IEN_TPU1_TGI1A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) IEN_TPU1_TGI1B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) IEN_TPU1_TGI1U=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) IEN_TPU1_TGI1V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) IEN_TPU2_TGI2A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) IEN_TPU2_TGI2B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) IEN_TPU2_TGI2U=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) IEN_TPU2_TGI2V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) IEN_TPU3_TGI3A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) IEN_TPU3_TGI3B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) IEN_TPU3_TGI3C=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) IEN_TPU3_TGI3D=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) IEN_TPU3_TGI3V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) IEN_TPU4_TGI4A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) IEN_TPU4_TGI4B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) IEN_TPU4_TGI4U=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) IEN_TPU4_TGI4V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) IEN_TPU5_TGI5A=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) IEN_TPU5_TGI5B=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) IEN_TPU5_TGI5U=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) IEN_TPU5_TGI5V=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) IEN_USB0_D0FIFO0=IEN2 IEN_USB0_D1FIFO0=IEN3 IEN_USB0_USBI0=BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) IEN_USB0_USBR0=IEN2 IEN_USBA_D0FIFO2=IEN0 IEN_USBA_D1FIFO2=IEN1 IEN_USBA_USBAR=IEN6 IEN_WDT_WUNI=IEN0 IER_AES_AESEND=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) IER_AES_AESRDY=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) IER_CAN0_RXF0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) IER_CAN0_RXM0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) IER_CAN0_TXF0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) IER_CAN0_TXM0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) IER_CAN1_RXF1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) IER_CAN1_RXM1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) IER_CAN1_TXF1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) IER_CAN1_TXM1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) IER_CAN2_RXF2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) IER_CAN2_RXM2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) IER_CAN2_TXF2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) IER_CAN2_TXM2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) IER_CMT2_CMI2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) IER_CMT3_CMI3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) IER_CMTW0_IC0I0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) IER_CMTW0_IC1I0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) IER_CMTW0_OC0I0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) IER_CMTW0_OC1I0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) IER_CMTW1_IC0I1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) IER_CMTW1_IC1I1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) IER_CMTW1_OC0I1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) IER_CMTW1_OC1I1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) IER_DES_DESEND=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) IER_ELC_ELSR18I=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) IER_ELC_ELSR19I=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) IER_EPTPC_IPLS=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) IER_MTU0_TGIA0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) IER_MTU0_TGIB0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) IER_MTU0_TGIC0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) IER_MTU0_TGID0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) IER_MTU0_TGIE0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) IER_MTU0_TGIF0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) IER_MTU0_TGIV0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) IER_MTU1_TGIA1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) IER_MTU1_TGIB1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) IER_MTU1_TGIU1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) IER_MTU1_TGIV1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) IER_MTU2_TGIA2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) IER_MTU2_TGIB2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) IER_MTU2_TGIU2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) IER_MTU2_TGIV2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) IER_MTU3_TGIA3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) IER_MTU3_TGIB3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) IER_MTU3_TGIC3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) IER_MTU3_TGID3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) IER_MTU3_TGIV3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) IER_MTU4_TGIA4=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) IER_MTU4_TGIB4=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) IER_MTU4_TGIC4=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) IER_MTU4_TGID4=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) IER_MTU4_TGIV4=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) IER_MTU5_TGIU5=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) IER_MTU5_TGIV5=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) IER_MTU5_TGIW5=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) IER_MTU6_TGIA6=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) IER_MTU6_TGIB6=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) IER_MTU6_TGIC6=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) IER_MTU6_TGID6=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) IER_MTU6_TGIV6=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) IER_MTU7_TGIA7=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) IER_MTU7_TGIB7=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) IER_MTU7_TGIC7=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) IER_MTU7_TGID7=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) IER_MTU7_TGIV7=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) IER_MTU8_TGIA8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) IER_MTU8_TGIB8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) IER_MTU8_TGIC8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) IER_MTU8_TGID8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) IER_MTU8_TGIU8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) IER_MTU8_TGIV8=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) IER_RNG_RNGEND=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) IER_RTC_CUP=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) IER_S12ADC0_S12ADI0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) IER_S12ADC0_S12GBADI0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) IER_S12ADC1_S12ADI1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) IER_S12ADC1_S12GBADI1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) IER_SHA_SHADEND=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) IER_SHA_SHAEND=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) IER_TMR0_CMIA0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) IER_TMR0_CMIB0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) IER_TMR0_OVI0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) IER_TMR1_CMIA1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) IER_TMR1_CMIB1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) IER_TMR1_OVI1=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) IER_TMR2_CMIA2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) IER_TMR2_CMIB2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) IER_TMR2_OVI2=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) IER_TMR3_CMIA3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) IER_TMR3_CMIB3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) IER_TMR3_OVI3=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) IER_TPU0_TGI0A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) IER_TPU0_TGI0B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) IER_TPU0_TGI0C=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) IER_TPU0_TGI0D=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) IER_TPU0_TGI0V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) IER_TPU1_TGI1A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) IER_TPU1_TGI1B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) IER_TPU1_TGI1U=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) IER_TPU1_TGI1V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) IER_TPU2_TGI2A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) IER_TPU2_TGI2B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) IER_TPU2_TGI2U=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) IER_TPU2_TGI2V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) IER_TPU3_TGI3A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) IER_TPU3_TGI3B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) IER_TPU3_TGI3C=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) IER_TPU3_TGI3D=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) IER_TPU3_TGI3V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) IER_TPU4_TGI4A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) IER_TPU4_TGI4B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) IER_TPU4_TGI4U=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) IER_TPU4_TGI4V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) IER_TPU5_TGI5A=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) IER_TPU5_TGI5B=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) IER_TPU5_TGI5U=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) IER_TPU5_TGI5V=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) IER_USB0_USBI0=BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) INT16_C(x)=(x) INT16_MAX=0x7fff INT16_MIN=(-0x7fff - _C2) INT32_C(x)=((x) + (INT32_MAX - INT32_MAX)) INT32_MAX=0x7fffffff INT32_MIN=(-0x7fffffff - _C2) INT64_C(x)=((x) + (INT64_MAX - INT64_MAX)) INT64_MAX=0x7fffffffffffffffLL INT64_MIN=(-0x7fffffffffffffffLL - _C2) INT8_C(x)=(x) INT8_MAX=0x7f INT8_MIN=(-0x7f - _C2) INTMAX_C(x)=INT64_C(x) INTMAX_MAX=0x7fffffffffffffffLL INTMAX_MIN=(-0x7fffffffffffffffLL - _C2) INTPTR_MAX=0x7fffffff INTPTR_MIN=(-INTPTR_MAX - _C2) int_exception(num)=_builtin_int_exception(num) INT_FAST16_MAX=0x7fff INT_FAST16_MIN=(-0x7fff - _C2) INT_FAST32_MAX=0x7fffffff INT_FAST32_MIN=(-0x7fffffff - _C2) INT_FAST64_MAX=0x7fffffffffffffffLL INT_FAST64_MIN=(-0x7fffffffffffffffLL - _C2) INT_FAST8_MAX=0x7f INT_FAST8_MIN=(-0x7f - _C2) INT_LEAST16_MAX=0x7fff INT_LEAST16_MIN=(-0x7fff - _C2) INT_LEAST32_MAX=0x7fffffff INT_LEAST32_MIN=(-0x7fffffff - _C2) INT_LEAST64_MAX=0x7fffffffffffffffLL INT_LEAST64_MIN=(-0x7fffffffffffffffLL - _C2) INT_LEAST8_MAX=0x7f INT_LEAST8_MIN=(-0x7f - _C2) IPR(x,y)=_IPR( _ ## x ## _ ## y ) IPR_AES_AESEND=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) IPR_AES_AESRDY=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) IPR_CAN0_RXF0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) IPR_CAN0_RXM0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) IPR_CAN0_TXF0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) IPR_CAN0_TXM0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) IPR_CAN1_RXF1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) IPR_CAN1_RXM1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) IPR_CAN1_TXF1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) IPR_CAN1_TXM1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) IPR_CAN2_RXF2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) IPR_CAN2_RXM2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) IPR_CAN2_TXF2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) IPR_CAN2_TXM2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) IPR_CMT2_CMI2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) IPR_CMT3_CMI3=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) IPR_CMTW0_IC0I0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) IPR_CMTW0_IC1I0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) IPR_CMTW0_OC0I0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) IPR_CMTW0_OC1I0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) IPR_CMTW1_IC0I1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) IPR_CMTW1_IC1I1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) IPR_CMTW1_OC0I1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) IPR_CMTW1_OC1I1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) IPR_DES_DESEND=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) IPR_ELC_ELSR18I=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) IPR_ELC_ELSR19I=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) IPR_EPTPC_IPLS=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) IPR_MTU0_TGIA0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) IPR_MTU0_TGIB0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) IPR_MTU0_TGIC0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) IPR_MTU0_TGID0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) IPR_MTU0_TGIE0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) IPR_MTU0_TGIF0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) IPR_MTU0_TGIV0=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) IPR_MTU1_TGIA1=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) IPR_MTU1_TGIB1=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) IPR_MTU1_TGIU1=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) IPR_MTU1_TGIV1=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) IPR_MTU2_TGIA2=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) IPR_MTU2_TGIB2=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) IPR_MTU2_TGIU2=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) IPR_MTU2_TGIV2=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) IPR_MTU3_TGIA3=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) IPR_MTU3_TGIB3=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) IPR_MTU3_TGIC3=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) IPR_MTU3_TGID3=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) IPR_MTU3_TGIV3=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) IPR_MTU4_TGIA4=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) IPR_MTU4_TGIB4=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) IPR_MTU4_TGIC4=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) IPR_MTU4_TGID4=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) IPR_MTU4_TGIV4=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) IPR_MTU5_TGIU5=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) IPR_MTU5_TGIV5=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) IPR_MTU5_TGIW5=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) IPR_MTU6_TGIA6=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) IPR_MTU6_TGIB6=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) IPR_MTU6_TGIC6=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) IPR_MTU6_TGID6=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) IPR_MTU6_TGIV6=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) IPR_MTU7_TGIA7=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) IPR_MTU7_TGIB7=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) IPR_MTU7_TGIC7=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) IPR_MTU7_TGID7=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) IPR_MTU7_TGIV7=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) IPR_MTU8_TGIA8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) IPR_MTU8_TGIB8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) IPR_MTU8_TGIC8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) IPR_MTU8_TGID8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) IPR_MTU8_TGIU8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) IPR_MTU8_TGIV8=BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) IPR_RNG_RNGEND=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) IPR_RTC_CUP=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) IPR_S12ADC0_S12ADI0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) IPR_S12ADC0_S12GBADI0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) IPR_S12ADC1_S12ADI1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) IPR_S12ADC1_S12GBADI1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) IPR_SHA_SHADEND=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) IPR_SHA_SHAEND=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) IPR_TMR0_CMIA0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) IPR_TMR0_CMIB0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) IPR_TMR0_OVI0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) IPR_TMR1_CMIA1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) IPR_TMR1_CMIB1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) IPR_TMR1_OVI1=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) IPR_TMR2_CMIA2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) IPR_TMR2_CMIB2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) IPR_TMR2_OVI2=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) IPR_TMR3_CMIA3=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) IPR_TMR3_CMIB3=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) IPR_TMR3_OVI3=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) IPR_TPU0_TGI0A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) IPR_TPU0_TGI0B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) IPR_TPU0_TGI0C=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) IPR_TPU0_TGI0D=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) IPR_TPU0_TGI0V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) IPR_TPU1_TGI1A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) IPR_TPU1_TGI1B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) IPR_TPU1_TGI1U=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) IPR_TPU1_TGI1V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) IPR_TPU2_TGI2A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) IPR_TPU2_TGI2B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) IPR_TPU2_TGI2U=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) IPR_TPU2_TGI2V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) IPR_TPU3_TGI3A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) IPR_TPU3_TGI3B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) IPR_TPU3_TGI3C=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) IPR_TPU3_TGI3D=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) IPR_TPU3_TGI3V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) IPR_TPU4_TGI4A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) IPR_TPU4_TGI4B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) IPR_TPU4_TGI4U=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) IPR_TPU4_TGI4V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) IPR_TPU5_TGI5A=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) IPR_TPU5_TGI5B=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) IPR_TPU5_TGI5U=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) IPR_TPU5_TGI5V=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) IPR_USB0_USBI0=BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) IR(x,y)=_IR( _ ## x ## _ ## y ) IR_AES_AESEND=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) IR_AES_AESRDY=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) IR_CAN0_RXF0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) IR_CAN0_RXM0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) IR_CAN0_TXF0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) IR_CAN0_TXM0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) IR_CAN1_RXF1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) IR_CAN1_RXM1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) IR_CAN1_TXF1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) IR_CAN1_TXM1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) IR_CAN2_RXF2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) IR_CAN2_RXM2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) IR_CAN2_TXF2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) IR_CAN2_TXM2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) IR_CMT2_CMI2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) IR_CMT3_CMI3=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) IR_CMTW0_IC0I0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) IR_CMTW0_IC1I0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) IR_CMTW0_OC0I0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) IR_CMTW0_OC1I0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) IR_CMTW1_IC0I1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) IR_CMTW1_IC1I1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) IR_CMTW1_OC0I1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) IR_CMTW1_OC1I1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) IR_DES_DESEND=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) IR_ELC_ELSR18I=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) IR_ELC_ELSR19I=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) IR_EPTPC_IPLS=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) IR_MTU0_TGIA0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) IR_MTU0_TGIB0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) IR_MTU0_TGIC0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) IR_MTU0_TGID0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) IR_MTU0_TGIE0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) IR_MTU0_TGIF0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) IR_MTU0_TGIV0=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) IR_MTU1_TGIA1=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) IR_MTU1_TGIB1=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) IR_MTU1_TGIU1=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) IR_MTU1_TGIV1=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) IR_MTU2_TGIA2=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) IR_MTU2_TGIB2=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) IR_MTU2_TGIU2=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) IR_MTU2_TGIV2=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) IR_MTU3_TGIA3=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) IR_MTU3_TGIB3=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) IR_MTU3_TGIC3=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) IR_MTU3_TGID3=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) IR_MTU3_TGIV3=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) IR_MTU4_TGIA4=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) IR_MTU4_TGIB4=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) IR_MTU4_TGIC4=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) IR_MTU4_TGID4=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) IR_MTU4_TGIV4=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) IR_MTU5_TGIU5=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) IR_MTU5_TGIV5=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) IR_MTU5_TGIW5=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) IR_MTU6_TGIA6=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) IR_MTU6_TGIB6=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) IR_MTU6_TGIC6=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) IR_MTU6_TGID6=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) IR_MTU6_TGIV6=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) IR_MTU7_TGIA7=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) IR_MTU7_TGIB7=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) IR_MTU7_TGIC7=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) IR_MTU7_TGID7=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) IR_MTU7_TGIV7=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) IR_MTU8_TGIA8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) IR_MTU8_TGIB8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) IR_MTU8_TGIC8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) IR_MTU8_TGID8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) IR_MTU8_TGIU8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) IR_MTU8_TGIV8=BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) IR_RNG_RNGEND=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) IR_RTC_CUP=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) IR_S12ADC0_S12ADI0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) IR_S12ADC0_S12GBADI0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) IR_S12ADC1_S12ADI1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) IR_S12ADC1_S12GBADI1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) IR_SHA_SHADEND=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) IR_SHA_SHAEND=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) IR_TMR0_CMIA0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) IR_TMR0_CMIB0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) IR_TMR0_OVI0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) IR_TMR1_CMIA1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) IR_TMR1_CMIB1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) IR_TMR1_OVI1=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) IR_TMR2_CMIA2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) IR_TMR2_CMIB2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) IR_TMR2_OVI2=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) IR_TMR3_CMIA3=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) IR_TMR3_CMIB3=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) IR_TMR3_OVI3=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) IR_TPU0_TGI0A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) IR_TPU0_TGI0B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) IR_TPU0_TGI0C=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) IR_TPU0_TGI0D=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) IR_TPU0_TGI0V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) IR_TPU1_TGI1A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) IR_TPU1_TGI1B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) IR_TPU1_TGI1U=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) IR_TPU1_TGI1V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) IR_TPU2_TGI2A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) IR_TPU2_TGI2B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) IR_TPU2_TGI2U=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) IR_TPU2_TGI2V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) IR_TPU3_TGI3A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) IR_TPU3_TGI3B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) IR_TPU3_TGI3C=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) IR_TPU3_TGI3D=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) IR_TPU3_TGI3V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) IR_TPU4_TGI4A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) IR_TPU4_TGI4B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) IR_TPU4_TGI4U=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) IR_TPU4_TGI4V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) IR_TPU5_TGI5A=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) IR_TPU5_TGI5B=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) IR_TPU5_TGI5U=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) IR_TPU5_TGI5V=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) IR_USB0_USBI0=BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) IS(x,y)=_IS( _ ## x ## _ ## y ) IS_CAC_FERRF=IS26 IS_CAC_MENDF=IS27 IS_CAC_OVFF=IS28 IS_CAN0_ERS0=IS0 IS_CAN1_ERS1=IS1 IS_CAN2_ERS2=IS2 IS_DOC_DOPCF=IS29 IS_EDMAC0_EINT0=IS4 IS_EDMAC1_EINT1=IS5 IS_EPTPC_MINT=IS0 IS_MMCIF_ACCIO=IS8 IS_MMCIF_CDETIO=IS6 IS_MMCIF_ERRIO=IS7 IS_PDC_PCERI=IS31 IS_PDC_PCFEI=IS30 IS_POE3_OEI1=IS9 IS_POE3_OEI2=IS10 IS_POE3_OEI3=IS11 IS_POE3_OEI4=IS12 IS_PRPEDMAC_PINT=IS1 IS_QSPI_QSPSSLI=IS24 IS_RIIC0_EEI0=IS14 IS_RIIC0_TEI0=IS13 IS_RIIC2_EEI2=IS16 IS_RIIC2_TEI2=IS15 IS_RSPI0_SPEI0=IS17 IS_RSPI0_SPII0=IS16 IS_S12AD0_S12CMPI0=IS20 IS_S12AD1_S12CMPI1=IS22 IS_SCI0_ERI0=IS1 IS_SCI0_TEI0=IS0 IS_SCI12_ERI12=IS17 IS_SCI12_SCIX0=IS18 IS_SCI12_SCIX1=IS19 IS_SCI12_SCIX2=IS20 IS_SCI12_SCIX3=IS21 IS_SCI12_TEI12=IS16 IS_SCI1_ERI1=IS3 IS_SCI1_TEI1=IS2 IS_SCI2_ERI2=IS5 IS_SCI2_TEI2=IS4 IS_SCI3_ERI3=IS7 IS_SCI3_TEI3=IS6 IS_SCI4_ERI4=IS9 IS_SCI4_TEI4=IS8 IS_SCI5_ERI5=IS11 IS_SCI5_TEI5=IS10 IS_SCI6_ERI6=IS13 IS_SCI6_TEI6=IS12 IS_SCI7_ERI7=IS15 IS_SCI7_TEI7=IS14 IS_SCIFA10_BRIF10=IS10 IS_SCIFA10_DRIF10=IS11 IS_SCIFA10_ERIF10=IS9 IS_SCIFA10_TEIF10=IS8 IS_SCIFA11_BRIF11=IS14 IS_SCIFA11_DRIF11=IS15 IS_SCIFA11_ERIF11=IS13 IS_SCIFA11_TEIF11=IS12 IS_SCIFA8_BRIF8=IS2 IS_SCIFA8_DRIF8=IS3 IS_SCIFA8_ERIF8=IS1 IS_SCIFA8_TEIF8=IS0 IS_SCIFA9_BRIF9=IS6 IS_SCIFA9_DRIF9=IS7 IS_SCIFA9_ERIF9=IS5 IS_SCIFA9_TEIF9=IS4 IS_SDHI_CACI=IS4 IS_SDHI_CDETI=IS3 IS_SDHI_SDACI=IS5 IS_SRC_CEF=IS2 IS_SRC_OVF=IS1 IS_SRC_PCERI=IS0 IS_SSI0_SSIF0=IS17 IS_SSI1_SSIF1=IS18 IWDT=(*(volatile struct st_iwdt __evenaccess *)0x88030) LED0=PORT0.PODR.BIT.B3 LED0_PDR=PORT0.PDR.BIT.B3 LED1=PORT0.PODR.BIT.B5 LED1_PDR=PORT0.PDR.BIT.B5 LED2=PORT2.PODR.BIT.B6 LED2_PDR=PORT2.PDR.BIT.B6 LED3=PORT2.PODR.BIT.B7 LED3_PDR=PORT2.PDR.BIT.B7 LED_OFF=(1) LED_ON=(0) LOCKING_H= LOWSRC_H= macl(data1,data2,count)=_builtin_macl(data1, data2, count) macw1(data1,data2,count)=_builtin_macw1(data1, data2, count) macw2(data1,data2,count)=_builtin_macw2(data1, data2, count) max(data1,data2)=_builtin_max(data1, data2) MCU_INFO= MCU_LOCKS_H= min(data1,data2)=_builtin_min(data1, data2) MMCIF=(*(volatile struct st_mmcif __evenaccess *)0x88500) MPC=(*(volatile struct st_mpc __evenaccess *)0x8C100) MPU=(*(volatile struct st_mpu __evenaccess *)0x86400) MSTP(x)=_MSTP( _ ## x ) MSTP_CAC=SYSTEM.MSTPCRC.BIT.MSTPC19 MSTP_CAN0=SYSTEM.MSTPCRB.BIT.MSTPB0 MSTP_CAN1=SYSTEM.MSTPCRB.BIT.MSTPB1 MSTP_CAN2=SYSTEM.MSTPCRB.BIT.MSTPB2 MSTP_CMT0=SYSTEM.MSTPCRA.BIT.MSTPA15 MSTP_CMT1=SYSTEM.MSTPCRA.BIT.MSTPA15 MSTP_CMT2=SYSTEM.MSTPCRA.BIT.MSTPA14 MSTP_CMT3=SYSTEM.MSTPCRA.BIT.MSTPA14 MSTP_CMTW0=SYSTEM.MSTPCRA.BIT.MSTPA1 MSTP_CMTW1=SYSTEM.MSTPCRA.BIT.MSTPA0 MSTP_CRC=SYSTEM.MSTPCRB.BIT.MSTPB23 MSTP_DA=SYSTEM.MSTPCRA.BIT.MSTPA19 MSTP_DMAC0=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC1=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC2=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC3=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC4=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC5=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC6=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC7=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DMAC=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_DOC=SYSTEM.MSTPCRB.BIT.MSTPB6 MSTP_DTC=SYSTEM.MSTPCRA.BIT.MSTPA28 MSTP_ECCRAM=SYSTEM.MSTPCRC.BIT.MSTPC6 MSTP_EDMAC0=SYSTEM.MSTPCRB.BIT.MSTPB15 MSTP_EDMAC1=SYSTEM.MSTPCRB.BIT.MSTPB14 MSTP_ELC=SYSTEM.MSTPCRB.BIT.MSTPB9 MSTP_EXDMAC0=SYSTEM.MSTPCRA.BIT.MSTPA29 MSTP_EXDMAC1=SYSTEM.MSTPCRA.BIT.MSTPA29 MSTP_EXDMAC=SYSTEM.MSTPCRA.BIT.MSTPA29 MSTP_GPT0=SYSTEM.MSTPCRA.BIT.MSTPA7 MSTP_GPT1=SYSTEM.MSTPCRA.BIT.MSTPA7 MSTP_GPT2=SYSTEM.MSTPCRA.BIT.MSTPA7 MSTP_GPT3=SYSTEM.MSTPCRA.BIT.MSTPA7 MSTP_GPT=SYSTEM.MSTPCRA.BIT.MSTPA7 MSTP_MMCIF=SYSTEM.MSTPCRD.BIT.MSTPD21 MSTP_MTU0=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU1=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU2=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU3=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU4=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU5=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU6=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU7=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU8=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_MTU=SYSTEM.MSTPCRA.BIT.MSTPA9 MSTP_PDC=SYSTEM.MSTPCRB.BIT.MSTPB22 MSTP_PPG0=SYSTEM.MSTPCRA.BIT.MSTPA11 MSTP_PPG1=SYSTEM.MSTPCRA.BIT.MSTPA10 MSTP_QSPI=SYSTEM.MSTPCRC.BIT.MSTPC23 MSTP_RAM0=SYSTEM.MSTPCRC.BIT.MSTPC0 MSTP_RIIC0=SYSTEM.MSTPCRB.BIT.MSTPB21 MSTP_RIIC2=SYSTEM.MSTPCRC.BIT.MSTPC17 MSTP_RSPI0=SYSTEM.MSTPCRB.BIT.MSTPB17 MSTP_S12AD1=SYSTEM.MSTPCRA.BIT.MSTPA16 MSTP_S12AD=SYSTEM.MSTPCRA.BIT.MSTPA17 MSTP_SCI0=SYSTEM.MSTPCRB.BIT.MSTPB31 MSTP_SCI12=SYSTEM.MSTPCRB.BIT.MSTPB4 MSTP_SCI1=SYSTEM.MSTPCRB.BIT.MSTPB30 MSTP_SCI2=SYSTEM.MSTPCRB.BIT.MSTPB29 MSTP_SCI3=SYSTEM.MSTPCRB.BIT.MSTPB28 MSTP_SCI4=SYSTEM.MSTPCRB.BIT.MSTPB27 MSTP_SCI5=SYSTEM.MSTPCRB.BIT.MSTPB26 MSTP_SCI6=SYSTEM.MSTPCRB.BIT.MSTPB25 MSTP_SCI7=SYSTEM.MSTPCRB.BIT.MSTPB24 MSTP_SCIFA10=SYSTEM.MSTPCRC.BIT.MSTPC25 MSTP_SCIFA11=SYSTEM.MSTPCRC.BIT.MSTPC24 MSTP_SCIFA8=SYSTEM.MSTPCRC.BIT.MSTPC27 MSTP_SCIFA9=SYSTEM.MSTPCRC.BIT.MSTPC26 MSTP_SDHI=SYSTEM.MSTPCRD.BIT.MSTPD19 MSTP_SMCI0=SYSTEM.MSTPCRB.BIT.MSTPB31 MSTP_SMCI12=SYSTEM.MSTPCRB.BIT.MSTPB4 MSTP_SMCI1=SYSTEM.MSTPCRB.BIT.MSTPB30 MSTP_SMCI2=SYSTEM.MSTPCRB.BIT.MSTPB29 MSTP_SMCI3=SYSTEM.MSTPCRB.BIT.MSTPB28 MSTP_SMCI4=SYSTEM.MSTPCRB.BIT.MSTPB27 MSTP_SMCI5=SYSTEM.MSTPCRB.BIT.MSTPB26 MSTP_SMCI6=SYSTEM.MSTPCRB.BIT.MSTPB25 MSTP_SMCI7=SYSTEM.MSTPCRB.BIT.MSTPB24 MSTP_SRC=SYSTEM.MSTPCRD.BIT.MSTPD23 MSTP_SSI0=SYSTEM.MSTPCRD.BIT.MSTPD15 MSTP_SSI1=SYSTEM.MSTPCRD.BIT.MSTPD14 MSTP_STBYRAM=SYSTEM.MSTPCRC.BIT.MSTPC7 MSTP_TEMPS=SYSTEM.MSTPCRB.BIT.MSTPB8 MSTP_TMR01=SYSTEM.MSTPCRA.BIT.MSTPA5 MSTP_TMR0=SYSTEM.MSTPCRA.BIT.MSTPA5 MSTP_TMR1=SYSTEM.MSTPCRA.BIT.MSTPA5 MSTP_TMR23=SYSTEM.MSTPCRA.BIT.MSTPA4 MSTP_TMR2=SYSTEM.MSTPCRA.BIT.MSTPA4 MSTP_TMR3=SYSTEM.MSTPCRA.BIT.MSTPA4 MSTP_TPU0=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_TPU1=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_TPU2=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_TPU3=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_TPU4=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_TPU5=SYSTEM.MSTPCRA.BIT.MSTPA13 MSTP_USB0=SYSTEM.MSTPCRB.BIT.MSTPB19 MSTP_USBA=SYSTEM.MSTPCRB.BIT.MSTPB12 MTU0=(*(volatile struct st_mtu0 __evenaccess *)0xC1290) MTU1=(*(volatile struct st_mtu1 __evenaccess *)0xC1290) MTU2=(*(volatile struct st_mtu2 __evenaccess *)0xC1292) MTU3=(*(volatile struct st_mtu3 __evenaccess *)0xC1200) MTU4=(*(volatile struct st_mtu4 __evenaccess *)0xC1200) MTU5=(*(volatile struct st_mtu5 __evenaccess *)0xC1A94) MTU6=(*(volatile struct st_mtu6 __evenaccess *)0xC1A00) MTU7=(*(volatile struct st_mtu7 __evenaccess *)0xC1A00) MTU8=(*(volatile struct st_mtu8 __evenaccess *)0xC1298) MTU=(*(volatile struct st_mtu __evenaccess *)0xC120A) nop()=_builtin_nop() NULL=_NULL offsetof(T,member)=((_CSTD size_t)&(((T *)0)->member)) PDC=(*(volatile struct st_pdc __evenaccess *)0xA0500) PLATFORM_DEFINED= PLATFORM_H= POE3=(*(volatile struct st_poe __evenaccess *)0x8C4C0) PORT0=(*(volatile struct st_port0 __evenaccess *)0x8C000) PORT1=(*(volatile struct st_port1 __evenaccess *)0x8C001) PORT2=(*(volatile struct st_port2 __evenaccess *)0x8C002) PORT3=(*(volatile struct st_port3 __evenaccess *)0x8C003) PORT4=(*(volatile struct st_port4 __evenaccess *)0x8C004) PORT5=(*(volatile struct st_port5 __evenaccess *)0x8C005) PORT6=(*(volatile struct st_port6 __evenaccess *)0x8C006) PORT7=(*(volatile struct st_port7 __evenaccess *)0x8C007) PORT8=(*(volatile struct st_port8 __evenaccess *)0x8C008) PORT9=(*(volatile struct st_port9 __evenaccess *)0x8C009) PORTA=(*(volatile struct st_porta __evenaccess *)0x8C00A) PORTB=(*(volatile struct st_portb __evenaccess *)0x8C00B) PORTC=(*(volatile struct st_portc __evenaccess *)0x8C00C) PORTD=(*(volatile struct st_portd __evenaccess *)0x8C00D) PORTE=(*(volatile struct st_porte __evenaccess *)0x8C00E) PORTF=(*(volatile struct st_portf __evenaccess *)0x8C00F) PORTG=(*(volatile struct st_portg __evenaccess *)0x8C010) PORTJ=(*(volatile struct st_portj __evenaccess *)0x8C012) PPG0=(*(volatile struct st_ppg0 __evenaccess *)0x881E6) PPG1=(*(volatile struct st_ppg1 __evenaccess *)0x881F0) PTPEDMAC=(*(volatile struct st_ptpedmac __evenaccess *)0xC0400) PTRDIFF_MAX=INT32_MAX PTRDIFF_MIN=INT32_MIN QSPI=(*(volatile struct st_qspi __evenaccess *)0x89E00) revl(data)=_builtin_revl(data) revw(data)=_builtin_revw(data) RIIC0=(*(volatile struct st_riic __evenaccess *)0x88300) RIIC2=(*(volatile struct st_riic __evenaccess *)0x88340) rmpab(init,count,addr1,addr2)=_builtin_rmpab(init, count, addr1, addr2) rmpal(init,count,addr1,addr2)=_builtin_rmpal(init, count, addr1, addr2) rmpaw(init,count,addr1,addr2)=_builtin_rmpaw(init, count, addr1, addr2) rolc(data)=_builtin_rolc(data) rorc(data)=_builtin_rorc(data) rotl(data,num)=_builtin_rotl(data, num) rotr(data,num)=_builtin_rotr(data, num) RSKRX64M_H= RSPI0=(*(volatile struct st_rspi __evenaccess *)0xD0100) RTC=(*(volatile struct st_rtc __evenaccess *)0x8C400) R_BSP_CONFIG_REF_HEADER_FILE= R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE= R_BSP_VERSION_MAJOR=(2) R_BSP_VERSION_MINOR=(80) S12AD1=(*(volatile struct st_s12ad1 __evenaccess *)0x89100) S12AD=(*(volatile struct st_s12ad __evenaccess *)0x89000) SCI0=(*(volatile struct st_sci0 __evenaccess *)0x8A000) SCI12=(*(volatile struct st_sci12 __evenaccess *)0x8B300) SCI1=(*(volatile struct st_sci0 __evenaccess *)0x8A020) SCI2=(*(volatile struct st_sci0 __evenaccess *)0x8A040) SCI3=(*(volatile struct st_sci0 __evenaccess *)0x8A060) SCI4=(*(volatile struct st_sci0 __evenaccess *)0x8A080) SCI5=(*(volatile struct st_sci0 __evenaccess *)0x8A0A0) SCI6=(*(volatile struct st_sci0 __evenaccess *)0x8A0C0) SCI7=(*(volatile struct st_sci0 __evenaccess *)0x8A0E0) SCIFA10=(*(volatile struct st_scifa __evenaccess *)0xD0040) SCIFA11=(*(volatile struct st_scifa __evenaccess *)0xD0060) SCIFA8=(*(volatile struct st_scifa __evenaccess *)0xD0000) SCIFA9=(*(volatile struct st_scifa __evenaccess *)0xD0020) SDHI=(*(volatile struct st_sdhi __evenaccess *)0x8AC00) setpsw_i()=_builtin_setpsw_i() set_acc(data)=_builtin_set_acc(data) SET_BIT_HIGH=(1) SET_BIT_LOW=(0) set_bpc(data)=_builtin_set_bpc(data) set_bpsw(data)=_builtin_set_bpsw(data) SET_BYTE_HIGH=(0xFF) SET_BYTE_LOW=(0x00) set_extb(data)=_builtin_set_extb(data) set_fintv(data)=_builtin_set_fintv(data) set_fpsw(data)=_builtin_set_fpsw(data) set_intb(data)=_builtin_set_intb(data) set_ipl(level)=_builtin_set_ipl(level) set_isp(data)=_builtin_set_isp(data) set_psw(data)=_builtin_set_psw(data) set_usp(data)=_builtin_set_usp(data) SIG_ATOMIC_MAX=INT32_MAX SIG_ATOMIC_MIN=INT32_MIN SIZE_MAX=UINT32_MAX SMCI0=(*(volatile struct st_smci0 __evenaccess *)0x8A000) SMCI12=(*(volatile struct st_smci0 __evenaccess *)0x8B300) SMCI1=(*(volatile struct st_smci0 __evenaccess *)0x8A020) SMCI2=(*(volatile struct st_smci0 __evenaccess *)0x8A040) SMCI3=(*(volatile struct st_smci0 __evenaccess *)0x8A060) SMCI4=(*(volatile struct st_smci0 __evenaccess *)0x8A080) SMCI5=(*(volatile struct st_smci0 __evenaccess *)0x8A0A0) SMCI6=(*(volatile struct st_smci0 __evenaccess *)0x8A0C0) SMCI7=(*(volatile struct st_smci0 __evenaccess *)0x8A0E0) SRC=(*(volatile struct st_src __evenaccess *)0x98000) SSI0=(*(volatile struct st_ssi __evenaccess *)0x8A500) SSI1=(*(volatile struct st_ssi __evenaccess *)0x8A540) SW1=PORT1.PIDR.BIT.B5 SW1_PDR=PORT1.PDR.BIT.B5 SW1_PMR=PORT1.PMR.BIT.B5 SW2=PORT1.PIDR.BIT.B2 SW2_PDR=PORT1.PDR.BIT.B2 SW2_PMR=PORT1.PMR.BIT.B2 SW3=PORT0.PIDR.BIT.B7 SW3_PDR=PORT0.PDR.BIT.B7 SW3_PMR=PORT0.PMR.BIT.B7 SW_ACTIVE=0 SYSTEM=(*(volatile struct st_system __evenaccess *)0x80000) TEMPS=(*(volatile struct st_temps __evenaccess *)0x8C500) TMR01=(*(volatile struct st_tmr01 __evenaccess *)0x88204) TMR0=(*(volatile struct st_tmr0 __evenaccess *)0x88200) TMR1=(*(volatile struct st_tmr1 __evenaccess *)0x88201) TMR23=(*(volatile struct st_tmr01 __evenaccess *)0x88214) TMR2=(*(volatile struct st_tmr0 __evenaccess *)0x88210) TMR3=(*(volatile struct st_tmr1 __evenaccess *)0x88211) TPU0=(*(volatile struct st_tpu0 __evenaccess *)0x88108) TPU1=(*(volatile struct st_tpu1 __evenaccess *)0x88108) TPU2=(*(volatile struct st_tpu2 __evenaccess *)0x8810A) TPU3=(*(volatile struct st_tpu3 __evenaccess *)0x8810A) TPU4=(*(volatile struct st_tpu4 __evenaccess *)0x8810C) TPU5=(*(volatile struct st_tpu5 __evenaccess *)0x8810C) TPUA=(*(volatile struct st_tpua __evenaccess *)0x88100) true=1 UINT16_C(x)=(x) UINT16_MAX=0xffff UINT32_C(x)=((x) + (UINT32_MAX - UINT32_MAX)) UINT32_MAX=0xffffffff UINT64_C(x)=((x) + (UINT64_MAX - UINT64_MAX)) UINT64_MAX=0xffffffffffffffffULL UINT8_C(x)=(x) UINT8_MAX=0xff UINTMAX_C(x)=UINT64_C(x) UINTMAX_MAX=0xffffffffffffffffULL UINTPTR_MAX=0xffffffff UINT_FAST16_MAX=0xffff UINT_FAST32_MAX=0xffffffff UINT_FAST64_MAX=0xffffffffffffffffULL UINT_FAST8_MAX=0xff UINT_LEAST16_MAX=0xffff UINT_LEAST32_MAX=0xffffffff UINT_LEAST64_MAX=0xffffffffffffffffULL UINT_LEAST8_MAX=0xff USB0=(*(volatile struct st_usb0 __evenaccess *)0xA0000) USB=(*(volatile struct st_usb __evenaccess *)0xA0400) USBA=(*(volatile struct st_usba __evenaccess *)0xD0400) va_arg(AP,TYPE)=(AP += ((sizeof(TYPE)+3)&~3), *((TYPE *)(AP - ((sizeof(TYPE)+3)&~3)))) va_copy(apd,aps)=_Vacopy(&(apd), aps) va_end(ap)= va_start(AP,LASTARG)=__builtin_va_start(AP) VECT(x,y)=_VECT( _ ## x ## _ ## y ) VECTTBL_HEADER_INC= VECT_AES_AESEND=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESEND) VECT_AES_AESRDY=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_AES_AESRDY) VECT_BSC_BUSERR=16 VECT_CAN0_RXF0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) VECT_CAN0_RXM0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) VECT_CAN0_TXF0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) VECT_CAN0_TXM0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) VECT_CAN1_RXF1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) VECT_CAN1_RXM1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) VECT_CAN1_TXF1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) VECT_CAN1_TXM1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) VECT_CAN2_RXF2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) VECT_CAN2_RXM2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) VECT_CAN2_TXF2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) VECT_CAN2_TXM2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) VECT_CMT0_CMI0=28 VECT_CMT1_CMI1=29 VECT_CMT2_CMI2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) VECT_CMT3_CMI3=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) VECT_CMTW0_CMWI0=30 VECT_CMTW0_IC0I0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) VECT_CMTW0_IC1I0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) VECT_CMTW0_OC0I0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) VECT_CMTW0_OC1I0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) VECT_CMTW1_CMWI1=31 VECT_CMTW1_IC0I1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) VECT_CMTW1_IC1I1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) VECT_CMTW1_OC0I1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) VECT_CMTW1_OC1I1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) VECT_DES_DESEND=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_DES_DESEND) VECT_DMAC_DMAC0I=120 VECT_DMAC_DMAC1I=121 VECT_DMAC_DMAC2I=122 VECT_DMAC_DMAC3I=123 VECT_DMAC_DMAC74I=124 VECT_ELC_ELSR18I=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) VECT_ELC_ELSR19I=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) VECT_EPTPC_IPLS=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) VECT_EXDMAC_EXDMAC0I=126 VECT_EXDMAC_EXDMAC1I=127 VECT_FCU_FIFERR=21 VECT_FCU_FRDYI=23 VECT_ICU_GROUPAL0=112 VECT_ICU_GROUPAL1=113 VECT_ICU_GROUPBE0=106 VECT_ICU_GROUPBL0=110 VECT_ICU_GROUPBL1=111 VECT_ICU_IRQ0=64 VECT_ICU_IRQ10=74 VECT_ICU_IRQ11=75 VECT_ICU_IRQ12=76 VECT_ICU_IRQ13=77 VECT_ICU_IRQ14=78 VECT_ICU_IRQ15=79 VECT_ICU_IRQ1=65 VECT_ICU_IRQ2=66 VECT_ICU_IRQ3=67 VECT_ICU_IRQ4=68 VECT_ICU_IRQ5=69 VECT_ICU_IRQ6=70 VECT_ICU_IRQ7=71 VECT_ICU_IRQ8=72 VECT_ICU_IRQ9=73 VECT_ICU_SWINT2=26 VECT_ICU_SWINT=27 VECT_IWDT_IWUNI=95 VECT_LVD1_LVD1=88 VECT_LVD2_LVD2=89 VECT_MMCIF_MBFAI=45 VECT_MTU0_TGIA0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) VECT_MTU0_TGIB0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) VECT_MTU0_TGIC0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) VECT_MTU0_TGID0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) VECT_MTU0_TGIE0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) VECT_MTU0_TGIF0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) VECT_MTU0_TGIV0=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIV0) VECT_MTU1_TGIA1=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) VECT_MTU1_TGIB1=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) VECT_MTU1_TGIU1=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIU1) VECT_MTU1_TGIV1=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIV1) VECT_MTU2_TGIA2=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) VECT_MTU2_TGIB2=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) VECT_MTU2_TGIU2=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIU2) VECT_MTU2_TGIV2=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIV2) VECT_MTU3_TGIA3=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) VECT_MTU3_TGIB3=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) VECT_MTU3_TGIC3=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) VECT_MTU3_TGID3=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) VECT_MTU3_TGIV3=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIV3) VECT_MTU4_TGIA4=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) VECT_MTU4_TGIB4=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) VECT_MTU4_TGIC4=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) VECT_MTU4_TGID4=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) VECT_MTU4_TGIV4=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIV4) VECT_MTU5_TGIU5=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) VECT_MTU5_TGIV5=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) VECT_MTU5_TGIW5=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) VECT_MTU6_TGIA6=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) VECT_MTU6_TGIB6=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) VECT_MTU6_TGIC6=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) VECT_MTU6_TGID6=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) VECT_MTU6_TGIV6=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIV6) VECT_MTU7_TGIA7=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) VECT_MTU7_TGIB7=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) VECT_MTU7_TGIC7=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) VECT_MTU7_TGID7=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) VECT_MTU7_TGIV7=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIV7) VECT_MTU8_TGIA8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) VECT_MTU8_TGIB8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) VECT_MTU8_TGIC8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) VECT_MTU8_TGID8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) VECT_MTU8_TGIU8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIU8) VECT_MTU8_TGIV8=BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIV8) VECT_OST_OST=125 VECT_PDC_PCDFI=97 VECT_PERIA_INTA208=208 VECT_PERIA_INTA209=209 VECT_PERIA_INTA210=210 VECT_PERIA_INTA211=211 VECT_PERIA_INTA212=212 VECT_PERIA_INTA213=213 VECT_PERIA_INTA214=214 VECT_PERIA_INTA215=215 VECT_PERIA_INTA216=216 VECT_PERIA_INTA217=217 VECT_PERIA_INTA218=218 VECT_PERIA_INTA219=219 VECT_PERIA_INTA220=220 VECT_PERIA_INTA221=221 VECT_PERIA_INTA222=222 VECT_PERIA_INTA223=223 VECT_PERIA_INTA224=224 VECT_PERIA_INTA225=225 VECT_PERIA_INTA226=226 VECT_PERIA_INTA227=227 VECT_PERIA_INTA228=228 VECT_PERIA_INTA229=229 VECT_PERIA_INTA230=230 VECT_PERIA_INTA231=231 VECT_PERIA_INTA232=232 VECT_PERIA_INTA233=233 VECT_PERIA_INTA234=234 VECT_PERIA_INTA235=235 VECT_PERIA_INTA236=236 VECT_PERIA_INTA237=237 VECT_PERIA_INTA238=238 VECT_PERIA_INTA239=239 VECT_PERIA_INTA240=240 VECT_PERIA_INTA241=241 VECT_PERIA_INTA242=242 VECT_PERIA_INTA243=243 VECT_PERIA_INTA244=244 VECT_PERIA_INTA245=245 VECT_PERIA_INTA246=246 VECT_PERIA_INTA247=247 VECT_PERIA_INTA248=248 VECT_PERIA_INTA249=249 VECT_PERIA_INTA250=250 VECT_PERIA_INTA251=251 VECT_PERIA_INTA252=252 VECT_PERIA_INTA253=253 VECT_PERIA_INTA254=254 VECT_PERIA_INTA255=255 VECT_PERIB_INTB128=128 VECT_PERIB_INTB129=129 VECT_PERIB_INTB130=130 VECT_PERIB_INTB131=131 VECT_PERIB_INTB132=132 VECT_PERIB_INTB133=133 VECT_PERIB_INTB134=134 VECT_PERIB_INTB135=135 VECT_PERIB_INTB136=136 VECT_PERIB_INTB137=137 VECT_PERIB_INTB138=138 VECT_PERIB_INTB139=139 VECT_PERIB_INTB140=140 VECT_PERIB_INTB141=141 VECT_PERIB_INTB142=142 VECT_PERIB_INTB143=143 VECT_PERIB_INTB144=144 VECT_PERIB_INTB145=145 VECT_PERIB_INTB146=146 VECT_PERIB_INTB147=147 VECT_PERIB_INTB148=148 VECT_PERIB_INTB149=149 VECT_PERIB_INTB150=150 VECT_PERIB_INTB151=151 VECT_PERIB_INTB152=152 VECT_PERIB_INTB153=153 VECT_PERIB_INTB154=154 VECT_PERIB_INTB155=155 VECT_PERIB_INTB156=156 VECT_PERIB_INTB157=157 VECT_PERIB_INTB158=158 VECT_PERIB_INTB159=159 VECT_PERIB_INTB160=160 VECT_PERIB_INTB161=161 VECT_PERIB_INTB162=162 VECT_PERIB_INTB163=163 VECT_PERIB_INTB164=164 VECT_PERIB_INTB165=165 VECT_PERIB_INTB166=166 VECT_PERIB_INTB167=167 VECT_PERIB_INTB168=168 VECT_PERIB_INTB169=169 VECT_PERIB_INTB170=170 VECT_PERIB_INTB171=171 VECT_PERIB_INTB172=172 VECT_PERIB_INTB173=173 VECT_PERIB_INTB174=174 VECT_PERIB_INTB175=175 VECT_PERIB_INTB176=176 VECT_PERIB_INTB177=177 VECT_PERIB_INTB178=178 VECT_PERIB_INTB179=179 VECT_PERIB_INTB180=180 VECT_PERIB_INTB181=181 VECT_PERIB_INTB182=182 VECT_PERIB_INTB183=183 VECT_PERIB_INTB184=184 VECT_PERIB_INTB185=185 VECT_PERIB_INTB186=186 VECT_PERIB_INTB187=187 VECT_PERIB_INTB188=188 VECT_PERIB_INTB189=189 VECT_PERIB_INTB190=190 VECT_PERIB_INTB191=191 VECT_PERIB_INTB192=192 VECT_PERIB_INTB193=193 VECT_PERIB_INTB194=194 VECT_PERIB_INTB195=195 VECT_PERIB_INTB196=196 VECT_PERIB_INTB197=197 VECT_PERIB_INTB198=198 VECT_PERIB_INTB199=199 VECT_PERIB_INTB200=200 VECT_PERIB_INTB201=201 VECT_PERIB_INTB202=202 VECT_PERIB_INTB203=203 VECT_PERIB_INTB204=204 VECT_PERIB_INTB205=205 VECT_PERIB_INTB206=206 VECT_PERIB_INTB207=207 VECT_QSPI_SPRI=42 VECT_QSPI_SPTI=43 VECT_RAM_RAMERR=18 VECT_RIIC0_RXI0=52 VECT_RIIC0_TXI0=53 VECT_RIIC2_RXI2=54 VECT_RIIC2_TXI2=55 VECT_RNG_RNGEND=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RNG_RNGEND) VECT_RSPI0_SPRI0=38 VECT_RSPI0_SPTI0=39 VECT_RTC_ALM=92 VECT_RTC_CUP=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) VECT_RTC_PRD=93 VECT_S12ADC0_S12ADI0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) VECT_S12ADC0_S12GBADI0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) VECT_S12ADC1_S12ADI1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) VECT_S12ADC1_S12GBADI1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) VECT_SCI0_RXI0=58 VECT_SCI0_TXI0=59 VECT_SCI12_RXI12=116 VECT_SCI12_TXI12=117 VECT_SCI1_RXI1=60 VECT_SCI1_TXI1=61 VECT_SCI2_RXI2=62 VECT_SCI2_TXI2=63 VECT_SCI3_RXI3=80 VECT_SCI3_TXI3=81 VECT_SCI4_RXI4=82 VECT_SCI4_TXI4=83 VECT_SCI5_RXI5=84 VECT_SCI5_TXI5=85 VECT_SCI6_RXI6=86 VECT_SCI6_TXI6=87 VECT_SCI7_RXI7=98 VECT_SCI7_TXI7=99 VECT_SCIFA10_RXIF10=104 VECT_SCIFA10_TXIF10=105 VECT_SCIFA11_RXIF11=114 VECT_SCIFA11_TXIF11=115 VECT_SCIFA8_RXIF8=100 VECT_SCIFA8_TXIF8=101 VECT_SCIFA9_RXIF9=102 VECT_SCIFA9_TXIF9=103 VECT_SDHI_SBFAI=44 VECT_SHA_SHADEND=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHADEND) VECT_SHA_SHAEND=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_SHA_SHAEND) VECT_SRC_IDEI=50 VECT_SRC_ODFI=51 VECT_SSI0_SSIRXI0=47 VECT_SSI0_SSITXI0=46 VECT_SSI1_SSIRTI1=48 VECT_TMR0_CMIA0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) VECT_TMR0_CMIB0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) VECT_TMR0_OVI0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) VECT_TMR1_CMIA1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) VECT_TMR1_CMIB1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) VECT_TMR1_OVI1=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) VECT_TMR2_CMIA2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) VECT_TMR2_CMIB2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) VECT_TMR2_OVI2=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) VECT_TMR3_CMIA3=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) VECT_TMR3_CMIB3=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) VECT_TMR3_OVI3=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) VECT_TPU0_TGI0A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) VECT_TPU0_TGI0B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) VECT_TPU0_TGI0C=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) VECT_TPU0_TGI0D=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) VECT_TPU0_TGI0V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0V) VECT_TPU1_TGI1A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) VECT_TPU1_TGI1B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) VECT_TPU1_TGI1U=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1U) VECT_TPU1_TGI1V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1V) VECT_TPU2_TGI2A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) VECT_TPU2_TGI2B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) VECT_TPU2_TGI2U=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2U) VECT_TPU2_TGI2V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2V) VECT_TPU3_TGI3A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) VECT_TPU3_TGI3B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) VECT_TPU3_TGI3C=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) VECT_TPU3_TGI3D=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) VECT_TPU3_TGI3V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3V) VECT_TPU4_TGI4A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) VECT_TPU4_TGI4B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) VECT_TPU4_TGI4U=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4U) VECT_TPU4_TGI4V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4V) VECT_TPU5_TGI5A=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) VECT_TPU5_TGI5B=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) VECT_TPU5_TGI5U=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5U) VECT_TPU5_TGI5V=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5V) VECT_USB0_D0FIFO0=34 VECT_USB0_D1FIFO0=35 VECT_USB0_USBI0=BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) VECT_USB0_USBR0=90 VECT_USBA_D0FIFO2=32 VECT_USBA_D1FIFO2=33 VECT_USBA_USBAR=94 VECT_WDT_WUNI=96 wait()=_builtin_wait() WCHAR_MAX=_WCMAX WCHAR_MIN=_WCMIN WDT=(*(volatile struct st_wdt __evenaccess *)0x88020) WINT_MAX=_WCMAX WINT_MIN=_WCMIN xchg(data1,data2)=_builtin_xchg(data1, data2) _ADDED_C_LIB=0 _ALT_NS=0 _ATEXIT_T=void _BITS_BYTE=8 _BSD_SIZE_T_DEFINED_= _BSP_PRV_DTCE(x,y)=DTCE_PERI ## x ## _INT ## x ## y _BSP_PRV_IEN(x)=__BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8) _BSP_PRV_INT_SELECT(x,y)=BSP_PRV_INT_ ## x ## _SELECT_ ## y _BSP_PRV_IPR(x,y)=IPR_PERI ## x ## _INT ## x ## y _BSP_PRV_IR(x,y)=IR_PERI ## x ## _INT ## x ## y _BSP_PRV_VECT(x,y)=VECT_PERI ## x ## _INT ## x ## y _BUILTIN= _C2=1 _C99= _CDECL= _CLR(x)=__CLR( x ) _COMPILER_TLS=0 _CPPLIB_VER=503 _CPS=1 _CRTIMP= _CSIGN=0 _CSTD= _C_LIB_DECL= _C_STD_BEGIN= _C_STD_END= _D0=3 _DBIAS=0x3fe _DLONG=0 _DOFF=4 _DTCE(x)=__DTCE( x ) _EN(x)=__EN( x ) _END_C_LIB_DECL= _END_EXTERN_C= _ERRNO= _EXFAIL=1 _EXTERN_C= _FBIAS=0x7e _FD_INVALID=(-1) _FD_NO(str)=((str)->_Handle) _FD_TYPE=signed char _FD_VALID(fd)=(0 <= (fd)) _FILE_OP_LOCKS=0 _FNAMAX=260 _FOFF=7 _FOPMAX=20 _FPP_TYPE=_FPP_RX _GLOBAL_LOCALE=0 _HAS_C9X=1 _HAS_C9X_IMAGINARY_TYPE=0 _HAS_EXCEPTIONS=1 _HAS_FIXED_POINT=1 _HAS_IMMUTABLE_SETS=1 _HAS_NAMESPACE=1 _HAS_POSIX_C_LIB=1 _HAS_STRICT_CONFORMANCE=0 _HAS_TR1=0 _HAS_TR1_DECLARATIONS=_HAS_TR1 _HAS_TRADITIONAL_IOSTREAMS=1 _HAS_TRADITIONAL_ITERATORS=0 _HAS_TRADITIONAL_POS_TYPE=0 _HAS_TRADITIONAL_STL=1 _H_C_LIB= _IEN(x)=__IEN( x ) _ILONG=1 _INTMAXT= _INTPTR=0 _INTPTR_T_DEFINED= _IOSTREAM_OP_LOCKS=0 _IPR(x)=__IPR( x ) _IR(x)=__IR( x ) _IS(x)=__IS( x ) _IS_EMBEDDED=0 _LBIAS=0x3fe _LLONG=0 _LLONG_MAX=0x7fffffffffffffffLL _Locksyslock(x)=(void)0 _LOCK_DEBUG=3 _LOCK_LOCALE=0 _LOCK_MALLOC=1 _LOCK_STREAM=2 _LOFF=4 _LONGLONG=long long _MACHINE= _MACH_PDT=long _MACH_SZT=unsigned long _MACRO= _MAX_EXP_DIG=8 _MAX_INT_DIG=32 _MAX_LOCK=4 _MAX_SIG_DIG=48 _MAYBE_LOCK=if (_Locktype == _LOCK_MALLOC || _Locktype == _LOCK_DEBUG) _MBMAX=8 _MEMBND=3U _MSTP(x)=__MSTP( x ) _MULTI_THREAD=0 _NO_MT= _NO_RETURN(fun)=void fun _NULL=0 _PTRDIFFT= _PTRDIFF_T= _PTRDIFF_T_DEFINED= _Restrict=restrict _RSIZE_MAX=((_Sizet)(-1) >> 1) _SIGABRT=6 _SIGMAX=44 _SIZET= _SIZE_T= _SIZE_T_DEFINED= _STD= _STDARG_H= _STDBOOL= _STDDEF= _STDINT= _STD_BEGIN= _STD_END= _STD_USING_BIT_TYPES= _STD_USING_INTPTR_T= _STD_USING_INT_TYPES= _STD_USING_PTRDIFF_T= _STD_USING_SIZE_T= _STD_USING_UINTPTR_T= _SYSCH(x)=x _TBIAS=((70 * 365LU + 17) * 86400) _TEMPLATE_STAT= _TLS_QUAL= _TNAMAX=16 _UINTPTR_T_DEFINED= _ULLONG_MAX=0xffffffffffffffffULL _ULONGLONG=unsigned long long _Unlocksyslock(x)=(void)0 _USE_EXISTING_SYSTEM_NAMES=1 _VECT(x)=__VECT( x ) _WCHART= _WCHAR_T_DEFINED= _WCMAX=0xffff _WCMIN=0 _XSTD= _X_STD_BEGIN= _X_STD_END= _YVALS= __bool_true_false_are_defined=1 __BSP_PRV_IEN(x)=___BSP_PRV_IEN(x) __builtin_constant_p(exp)=0 __builtin_offsetof(T,m)=((size_t) &((T *)0)->m) __builtin_types_compatible_p(x,y)=__builtin_types_compatible_p(sizeof(x),sizeof(y)) __builtin_va_arg(ap,type)=*(typeof(type) *)ap __CDT_PARSER__=1 __CLR(x)=ICU.GCR ## x.BIT.CLR ## x __complex__=_Complex __COUNTER__=0 __DATE__="9ŒŽ 25 2017" __DTCE(x)=ICU.DTCER[ DTCE ## x ].BIT.DTCE __EN(x)=ICU.GEN ## x.BIT.EN ## x __extension__= __FILE__="file" __IEN(x)=ICU.IER[ IER ## x ].BIT.IEN ## x __imag__=(int) __int8_t_defined= __IPR(x)=ICU.IPR[ IPR ## x ].BIT.IPR __IR(x)=ICU.IR[ IR ## x ].BIT.IR __IS(x)=ICU.GRP ## x.BIT.IS ## x __LINE__=1 __MSTP(x)=MSTP ## x __null=(void *)0 __offsetof__(x)=(x) __real__=(int) __RX64MIODEFINE_HEADER__= __stdcall= __STDC_IEC_559_COMPLEX__=1 __STDC_IEC_559__=1 __STDC_ISO_10646__=200009L __STDC_LIB_EXT1__=200509L __STDC_WANT_LIB_EXT1__=0 __STDC_WANT_SAFER_LIB__=0 __STDC__=1 __thread= __TIME__="06:16:06" __VECT(x)=VECT ## x ___BSP_PRV_IEN(x)=IEN ## x Macro definitions (from files actually parsed): BSP_DECLARE_STACK= FPSW_init=(0x00000000) FPU_DENOM=0x00000100 FPU_ROUND=0x00000000 PSW_init=(0x00010000) PSW_init=(0x00030000) Written on Mon Sep 25 06:16:06 JST 2017