SPIバッファのインクリメントについて

上記のように設定して、Generate Project contentボタンからファイルを生成しました。

r_spi.cおよびr_spi.hに独自の関数を作り、SPDレジスタに直接書き込む方法で、複数データをバースト転送することを試みています。

R_SPI_OPenの関数の中で、r_spi_hw_configのみを下記のように書き換えました。

static void r_spi_hw_config (spi_instance_ctrl_t * p_ctrl)
{

uint32_t spcr = 0;
uint32_t sslp = 0;
uint32_t sppcr = 0;
uint32_t spcr2 = 0;
uint32_t spckd = 0;
uint32_t sslnd = 0;
uint32_t spnd = 0;
uint32_t spcmd0 = 0;
uint32_t spdcr = 0;
uint32_t spdcr2 = 0;
uint32_t mrckd = 0;
uint32_t spdrcr = 0;

spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend);

/* Enable Receive Buffer Full interrupt. */
spcr |= R_SPI0_SPCR_SPRIE_Msk;

/* The TXI interrupt is not needed when TRANSMIT_FROM_RXI_ISR optimization is enabled. */
#if SPI_TRANSMIT_FROM_RXI_ISR == 0

/* Enable Transmit Buffer Empty interrupt. */
spcr |= R_SPI0_SPCR_SPTIE_Msk;
#endif

/* Enable Error interrupt. */
spcr |= R_SPI0_SPCR_SPEIE_Msk;

/* Enable Transmit end interrupt */
spcr |= R_SPI0_SPCR_CENDIE_Msk;

/* Configure Master Mode setting. */
spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR_MSTR_Pos;

/* Enable SCK Auto Stop setting in order to prevent RX Overflow in Master Mode */
spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR_SCKASE_Pos;

/* Configure Synchronization Circuit Bypass. */
spcr |= (uint32_t) p_extend->sync_bypass << R_SPI0_SPCR_BPEN_Pos;

/* Configure CPHA setting. */
spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI0_SPCMD_CPHA_Pos;

/* Configure CPOL setting. */
spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_polarity << R_SPI0_SPCMD_CPOL_Pos;

/* Configure Bit Order (MSB,LSB) */
spcmd0 |= (uint32_t) p_ctrl->p_cfg->bit_order << R_SPI0_SPCMD_LSBF_Pos;

if (p_ctrl->p_cfg->p_transfer_tx)
{
/* Transmit Buffer Empty IRQ must be enabled for DMAC even if TRANSMIT_FROM_RXI is enabled. */
spcr |= R_SPI0_SPCR_SPTIE_Msk;
}

if (SPI_SSL_MODE_SPI == p_extend->spi_clksyn)
{
#if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 1

/* Configure SSL Level Keep Setting. */
spcmd0 |= R_SPI0_SPCMD_SSLKP_Msk;
#endif

/* Configure 4-Wire Mode Setting. */
spcr &= ~R_SPI0_SPCR_SPMS_Msk;
}
else
{
/* Configure 3-Wire Mode Setting. */
spcr |= R_SPI0_SPCR_SPMS_Msk;
}

/* Configure Full Duplex or TX Only Setting. */
spcr &= (uint32_t) ~(p_extend->spi_comm << R_SPI0_SPCR_SPRIE_Pos),
spcr |=
(uint32_t) ((p_extend->spi_comm << R_SPI0_SPCR_TXMD_Pos) |
(p_extend->spi_comm << R_SPI0_SPCR_SPTIE_Pos));

/* Configure SSLn polarity setting. */
sslp &= ~0x0FU;
sslp |= (uint32_t) p_extend->ssl_polarity << p_extend->ssl_select;

/* Configure SSLn setting. (SSL0, SSL1, SSL2, SSL3)*/
spcmd0 &= ~R_SPI0_SPCMD_SSLA_Msk;
spcmd0 |= (uint32_t) p_extend->ssl_select << R_SPI0_SPCMD_SSLA_Pos;

if (SPI_MOSI_IDLE_VALUE_FIXING_DISABLE != p_extend->mosi_idle)
{
/* Enable mosi value fixing */
sppcr |= R_SPI0_SPPCR_MOIFE_Msk;

if (SPI_MOSI_IDLE_VALUE_FIXING_HIGH == p_extend->mosi_idle)
{
sppcr |= R_SPI0_SPPCR_MOIFV_Msk;
}
}

if (SPI_PARITY_MODE_DISABLE != p_extend->parity)
{
/* Enable Parity Mode. */
spcr |= R_SPI0_SPCR_SPPE_Msk;

if (SPI_PARITY_MODE_ODD == p_extend->parity)
{
/* Configure ODD Parity Setting. */
spcr |= R_SPI0_SPCR_SPOE_Msk;
}
}

/* Configure byte swapping for 16/32-Bit mode. */
spdcr |= p_extend->byte_swap;

/* Configure the Bit Rate Division Setting */
spcmd0 |= (uint32_t) p_extend->spck_div.brdv << R_SPI0_SPCMD_BRDV_Pos;

/* Enable all delay settings. */
if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode)
{
/* Note that disabling delay settings is same as setting delay to 1. */
spcmd0 |= (uint32_t) R_SPI0_SPCMD_SPNDEN_Msk | R_SPI0_SPCMD_SLNDEN_Msk | R_SPI0_SPCMD_SCKDEN_Msk | R_SPI0_SPCMD_SPB_Msk;

spckd = p_extend->spck_delay;
sslnd = p_extend->ssl_negation_delay;
spnd = p_extend->next_access_delay;
}

/* Sets the receive FIFO threshold and the transmit FIFO threshold */
spdcr2 =
(uint32_t) ((p_extend->transmit_fifo_threshold <<
R_SPI0_SPDCR2_TTRG_Pos) | (p_extend->receive_fifo_threshold << R_SPI0_SPDCR2_RTRG_Pos));

/* Sets the received data ready detection timing */
spdrcr = p_extend->receive_data_ready_detect_adjustment;

/* Power up the SPI module. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
R_BSP_MODULE_START(FSP_IP_SPI, p_ctrl->p_cfg->channel);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);

spcmd0 = 0x0207e080 ;

/* Write registers */

p_ctrl->p_regs->SSLP = (uint8_t) sslp;
p_ctrl->p_regs->SPPCR = (uint8_t) sppcr;
p_ctrl->p_regs->SPBR = p_extend->spck_div.spbr;
p_ctrl->p_regs->SPDCR = (uint16_t) 0x020A;
p_ctrl->p_regs->SPCKD = (uint8_t) spckd;
p_ctrl->p_regs->SSLND = (uint8_t) sslnd;
p_ctrl->p_regs->SPND = (uint8_t) spnd;
p_ctrl->p_regs->SPCR2 = (uint8_t) spcr2;
p_ctrl->p_regs->SPSCR_b.SPSLN = 2;
p_ctrl->p_regs->SPCMD[0] = spcmd0;
p_ctrl->p_regs->SPCMD[1] = spcmd0;
p_ctrl->p_regs->SPCMD[2] = spcmd0;
p_ctrl->p_regs->SPDCR2 = (uint16_t) 0x0202;
p_ctrl->p_regs->MRCKD = (uint8_t) mrckd;
p_ctrl->p_regs->SPDRCR = (uint8_t) spdrcr;
p_ctrl->p_regs->SPCR = spcr;

p_ctrl->p_regs->SPSRC = (R_SPI0_SPSRC_SPDRFC_Msk) | (R_SPI0_SPSRC_OVRFC_Msk) | (R_SPI0_SPSRC_MODFC_Msk) |
(R_SPI0_SPSRC_PERFC_Msk) | (R_SPI0_SPSRC_UDRFC_Msk);

/* Clear the FIFO status */
p_ctrl->p_regs->SPFCR = R_SPI0_SPFCR_SPFRST_Msk;

/* Disable the transmit end interrupt */
p_ctrl->p_regs->SPCR_b.CENDIE = 0;
p_ctrl->p_regs->SPDCR_b.SPRDTD=0;//0->受信バッファ　1->送信バッファ

/* Enable the SPI Transfer. */

p_ctrl->p_regs->SPCR_b.SPE=1;

//SPD_Write//
p_ctrl->p_regs->SPDR_b.SPD=5;

p_ctrl->p_regs->SPDR_b.SPD=3;

p_ctrl->p_regs->SPDR_b.SPD=1;
p_ctrl->p_regs->SPDR_b.SPD=2;

#if BSP_FEATURE_SPI_HAS_SPCR3 == 1
p_ctrl->p_regs->SPCR3 = R_SPI0_SPCR3_CENDIE_Msk;
#endif
}

変更したかったのはSPSCR.SPSLN、SPDCR2.RTRG、SPDCR2.TTRGのみです。

SPDに5, 3, 1, 2をそれぞれ8bitで送信しています。

まず1行ずつ送信を行うと、

PSCR.SPSLNは2のため、3行目(1)のデータを送信したら、SPSSR.SPCPが0に戻り、

スレーブがないため、TFDNは4から3,2..と下がっていき、RFDNは0のままというのが期待値ですが、

しかし、現状はTFDNが4のままで、SPRFSR.RFDNが0からインクリメントしていきます。

出力が出ないのも解決したいのですが、まずはバッファにきちんとデータを格納したいです。

長くて申し訳ないのですが、お分かりになる方、助けていただけますと幸いです。