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GPT PWM

king

我想在EK-RA6M3板子上输出一个PWM波，频率是4Mhz的，但是我最多只能设置为4Mhz，然后频率需要微调，比如4.01M，4.02M（步进10Khz左右的PWM），请问要怎么设置才能设置4.01Mhz呢？我这边只能设置为4Mhz。

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  • 0

    6m3上面的gpt时钟源PCLKD是120Mhz的，所以我periodset设置了30输出4M的PWM

  • 0 in reply to king
    120M->变4M, 设置的数值是30,  其他频率要设置的数值x = 4.01,  就是count = x*30/4, 得到的浮点值30.074再转换成十六进制 还是30, 所以是分辨率不够造成的, 
    #define GPT_EXAMPLE_MSEC_PER_SEC (1000)
    #define GPT_EXAMPLE_DESIRED_PERIOD_MSEC (20)
    /* This example shows how to calculate a new period value at runtime. */
    void gpt_period_calculation_example (void)
    {
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
    * - If the PCLKD frequency has not changed since reset, the source clock frequency is
    * BSP_STARTUP_PCLKD_HZ >> timer_cfg_t::source_div
    * - Use the R_GPT_InfoGet function (it accounts for the divider).
    * - Calculate the current PCLKD frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) and right shift
    * by timer_cfg_t::source_div.
    *
    * This example uses the 3rd option (R_FSP_SystemClockHzGet).
    */
    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> g_timer0_cfg.source_div;
    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
    * desired period is larger than UINT32_MAX / pclkd_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
    (uint32_t) (((uint64_t) pclkd_freq_hz * GPT_EXAMPLE_DESIRED_PERIOD_MSEC) / GPT_EXAMPLE_MSEC_PER_SEC);
    /* Set the calculated period. */
    err = R_GPT_PeriodSet(&g_timer0_ctrl, period_counts);
    assert(FSP_SUCCESS == err);
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  • 0 in reply to king
    120M->变4M, 设置的数值是30,  其他频率要设置的数值x = 4.01,  就是count = x*30/4, 得到的浮点值30.074再转换成十六进制 还是30, 所以是分辨率不够造成的, 
    #define GPT_EXAMPLE_MSEC_PER_SEC (1000)
    #define GPT_EXAMPLE_DESIRED_PERIOD_MSEC (20)
    /* This example shows how to calculate a new period value at runtime. */
    void gpt_period_calculation_example (void)
    {
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
    * - If the PCLKD frequency has not changed since reset, the source clock frequency is
    * BSP_STARTUP_PCLKD_HZ >> timer_cfg_t::source_div
    * - Use the R_GPT_InfoGet function (it accounts for the divider).
    * - Calculate the current PCLKD frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) and right shift
    * by timer_cfg_t::source_div.
    *
    * This example uses the 3rd option (R_FSP_SystemClockHzGet).
    */
    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> g_timer0_cfg.source_div;
    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
    * desired period is larger than UINT32_MAX / pclkd_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
    (uint32_t) (((uint64_t) pclkd_freq_hz * GPT_EXAMPLE_DESIRED_PERIOD_MSEC) / GPT_EXAMPLE_MSEC_PER_SEC);
    /* Set the calculated period. */
    err = R_GPT_PeriodSet(&g_timer0_ctrl, period_counts);
    assert(FSP_SUCCESS == err);
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