Applilet EZ PL for RL78 V1.0J, V2.00J を試してみました。
デジタル回路版電子ブロックという感じで興味深いツールと思いましたが、少々使いづらい点もあったので改善要望として挙げておきます。
> 本ツールは評価版です。本ツールに関するテクニカルサポートは受け付けておりません。
と明記されていることは理解しており、返答等を求めているものではありません。
・ROM 消費量が多い
Applilet EZ PL for RL78 V2.00J + CC-RL V1.04.00 を使用し、R5F10Y16ASP(RL78/G10 10ピン ROM 2kB)をターゲットとして選択し、ちょっと何かを作るとすると簡単に 2kB のサイズを超えてしまい ます。
R5F10Y17ASP(RL78/G10 10ピン ROM 4kB)にターゲットを変更して「生成」をしなおすと成功したりしますが、実際のところターゲット変更は手軽にできるものではないのでできれば避けたいところです。
試したプロジェクトの .map ファイルを見てみると、
_MOV1_ 0000013b 0 none ,g 0 _NOT1_ 0000013c 0 none ,g 0 _WAIT 00000143 0 none ,g 0 _Port_Set 000001b9 0 none ,g 0 _MD_INTTM00 0000020c 0 none ,g 0 _MD_INTP0 0000021d 0 none ,g 0 _MD_INTP1 0000021f 0 none ,g 0 _ANDF 0000047f 0 none ,g 0 _ORF 0000048d 0 none ,g 0 _XORF 0000049b 0 none ,g 0 _IC_74HC138_Judge_Enable 000004a2 0 none ,g 0 _IC_74HC138_Out_Y0 00000500 0 none ,g 0 _IC_74HC138_Out_Y1 0000050b 0 none ,g 0 _IC_74HC138_Out_Y2 00000516 0 none ,g 0 _IC_74HC138_Out_Y3 00000524 0 none ,g 0 _IC_74HC138_Out_Y4 00000532 0 none ,g 0 _IC_74HC138_Out_Y5 00000540 0 none ,g 0 _IC_74HC138_Out_Y6 0000054e 0 none ,g 0 _IC_74HC138_Out_Y7 0000055c 0 none ,g 0 _PWM_CH2_Init 000008f6 0 none ,g 0 _PWM_CH3_Init 000008f7 0 none ,g 0 _PWM_Out_CH2 000008f8 0 none ,g 0 _PWM_Out_CH3 000008f9 0 none ,g 0
とりあえずこれだけの使用されていない関数が無駄に ROM に配置されていました。ROM の消費量が多いことの一因ではないかと思います。
Applilet EZ PL for RL78 と併せて使用したツールチェーン CC-RL にリンク時に未使用オブジェクト(関数、変数、定数)を削除する機能がないことが直接の原因とは思いますが、それであれば、Applilet EZ PL for RL78 のライブラリとして定義される関数や変数はソースレベルでバラバラにしてコンパイルし一旦ライブラリファイルにまとめ、それをリンクすることで無駄なオブジェクトのリンクを避ける方法もあるのではないでしょうか。
訂正 後の Reply で NoMaYさんの指摘されている CC-RL の未参照オブジェクトを削除する機能を上手く使用すればサイズ縮小に役立つのではないでしょうか。
何らかの条件によりリンカの -Optimize=SYmbol_delete が意図通りに機能しないことがあるようです。CS+の設定やcstart.asmの記述を弄っていたら以下のように削除されることもあることに気付きました。(当方特有の事情によりCC-RL V1.02を使用) (条件を絞り込み中)
*** Delete Symbols ***SYMBOL SIZE INFO_WDT_Reset 4 func ,g_MOV1_ 1 func ,g_NOT1_ 7 func ,g_WAIT d func ,g_WDT_Init 1 func ,g_Clock_Init 1 func ,g_DGIN_Counter_Clear 4 func ,g_CLK_Counter_Clear 4 func ,g_IC74HC166_Counter_Clear 4 func ,g以後省略
*** Delete Symbols ***
SYMBOL SIZE INFO
_WDT_Reset
4 func ,g
_MOV1_
1 func ,g
_NOT1_
7 func ,g
_WAIT
d func ,g
_WDT_Init
_Clock_Init
_DGIN_Counter_Clear
_CLK_Counter_Clear
_IC74HC166_Counter_Clear
以後省略
> 何らかの条件によりリンカの -Optimize=SYmbol_delete が意図通りに機能しないことがあるようです。
Applilet EZ PL for RL78 Ver.2.00 でのビルドの際には
となっていたので、これを
にしてビルドし直してみたところ、特にサイズに変わりはなく未使用変数や関数の削除は行われている様子はありません。CC-RL の使用法をよく理解していないのか、あるいは不具合かはまだ不明です。
リンカの SYmbol_delete が機能するパターン1つと機能しないパターン2つを作ってみました。(これらの例ではcstart.asmの記述を弄りませんでした。) Applilet EZ PL for RL78 V2.0でビルドした時のLOCファイルとMAPファイルは以下の通りです。MyLogic.loc
; Applilet EZ PL for RL78 ; PANEL LOCATION ; INPUT I_05:DGIN H,P13.7,0 ;3pin ; PROCESS 0105:LINE LR 0205:LINE LR 0305:LINE LR 0404:CLK R1,0.50S 0405:LINE LR 0504:LINE LR 0505:LINE LR 0601:ON R 0602:ON R 0603:OFF R 0604:LINE LR 0605:LINE LR 0606:OFF R 0607:OFF R 0608:OFF R 0609:OFF R 0610:OFF R 0611:OFF R 0612:OFF R 0613:OFF R 0701:IC74HC166 L13R1 0801:LINE LR 0901:LINE LR 1001:LINE LR 1101:LINE LR 1201:LINE LR 1301:LINE LR 1401:LINE LR 1501:LINE LR 1601:LINE LR ; OUTPUT O_01:DGO H,P0.0 ;6pin ; ;PORTSTART ;P0.0,2,0,1 ;P0.1,3,0,1 ;P0.2,3,0,1 ;P0.3,3,0,1 ;P0.4,1,0,1 ;P4.0,3,0,1 ;P12.5,4,0,2 ;P13.7,4,0,0 ;PORTEND ; ;UARTSTART ;UART0,12,8,0,,1 ;UART1,12,8,0,,1 ;UART6,12,8,1,1,1 ;UARTEND ; ;PWMSTART ;PWMCHAN,1 ;PWMFREQ,100 ;PWMEND ;
Renesas Optimizing Linker (W2.04.00 ) 14-May-2017 07:15:05 *** Options *** -SUbcommand=MyLogic.plk -SECURITY_ID=00000000000000000000 -DEVICE="E:\tools\micom\Renesas\Applilet EZ PL for RL78 V2.00\Tools\BIN\..\..\Tools\DEV\DR5F10Y47.DVF" -NODEBug -NOOPtimize -OUtput="MyLogic.abs" -LIBrary="E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4s.lib" -LIBrary="E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4r.lib" -LISt -SHow=ALL -AUTO_SECTION_LAYOUT -ROm=.data=.dataR -ROm=.sdata=.sdataR -NOMessage -MEMory=High -NOLOgo -Total_size -Input="obj\cstart.obj" -Input="obj\opt_byte.obj" -Input="obj\main.obj" -Input="obj\common.obj" -Input="obj\timer.obj" -Input="obj\int.obj" -Input="obj\port.obj" -Input="obj\watchdogtimer.obj" -Input="obj\system.obj" -Input="obj\systeminit.obj" -Input="obj\panel.obj" -Input="obj\digitalio.obj" -Input="obj\clk.obj" -Input="obj\74hc.obj" -END *** Error information *** *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000090 f 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .textf 000000c4 000000c4 0 1 .text 000000ce 00000588 4bb 1 .RLIB 00000589 000005ee 66 1 .bss 000ffce0 000ffced e 2 .dataR 000ffcee 000ffcfc f 2 .stack_bss 000ffcfe 000ffd3d 40 2 .sbss 000ffe20 000ffe28 9 2 .sdataR 000ffe2a 000ffe2a 0 2 *** Total Section Size *** RAMDATA SECTION: 00000066 Byte(s) ROMDATA SECTION: 0000009d Byte(s) PROGRAM SECTION: 00000521 Byte(s) *** Symbol List *** SECTION= FILE= START END SIZE SYMBOL ADDR SIZE INFO COUNTS OPT STRUCT SIZE MEMBER ADDR SIZE INFO SECTION=.vect FILE=rlink_generates_01 00000000 0000007f 80 SECTION=.data FILE=obj\panel.obj 00000082 0000008e d FILE=obj\74hc.obj 00000090 00000090 1 SECTION=.option_byte FILE=obj\opt_byte.obj 000000c0 000000c3 4 SECTION=.security_id FILE=rlink_generates_02 000000c4 000000cd a SECTION=.text FILE=obj\cstart.obj 000000ce 00000110 43 _start 000000ce 0 none ,g 0 _exit 0000010f 0 none ,g 1 FILE=obj\main.obj 00000111 00000123 13 _main 00000111 0 none ,g 1 _main_loop 00000119 0 none ,g 1 FILE=obj\common.obj 00000124 000001ea c7 _MOV1_ 00000124 0 none ,g 0 _NOT1_ 00000125 0 none ,g 0 _WAIT 0000012c 0 none ,g 0 _BitMemGet 00000139 0 none ,g 3 _ByteMemGet 00000156 0 none ,g 2 _BitMemSet 0000015e 0 none ,g 3 _ByteMemSet 00000199 0 none ,g 4 _Port_Set 000001a2 0 none ,g 1 _Port_Get 000001ce 0 none ,g 1 FILE=obj\timer.obj 000001eb 00000258 6e _MD_INTTM00 000001eb 0 none ,g 0 _TM00_Init 000001fc 0 none ,g 1 _TM_10ms 0000022b 0 none ,g 1 FILE=obj\int.obj 00000259 0000028d 35 _MD_INTP0 00000259 0 none ,g 0 _MD_INTP1 0000025b 0 none ,g 0 _MD_INTP2 0000025d 0 none ,g 0 _MD_INTP3 0000025f 0 none ,g 0 _MD_INTIT 00000261 0 none ,g 0 _INT_Init 00000263 0 none ,g 1 FILE=obj\port.obj 0000028e 000002aa 1d _PORT_Init 0000028e 0 none ,g 1 FILE=obj\watchdogtimer.obj 000002ab 000002af 5 _WDT_Init 000002ab 0 none ,g 1 _WDT_Reset 000002ac 0 none ,g 1 FILE=obj\system.obj 000002b0 000002b0 1 _Clock_Init 000002b0 0 none ,g 1 FILE=obj\systeminit.obj 000002b1 000002cf 1f _SystemInit 000002b1 0 none ,g 1 _hdwinit 000002c6 0 none ,g 2 FILE=obj\panel.obj 000002d0 00000331 62 _panel_init0 000002d0 0 none ,g 1 _panel 000002dd 0 none ,g 1 FILE=obj\digitalio.obj 00000332 000003ee bd _DGOUT_setValue 00000332 0 none ,g 1 _DGIN_Initialize 00000357 0 none ,g 1 _DGIN_Counter_Clear 00000369 0 none ,g 1 _DGIN_getValue 0000036d 0 none ,g 1 _DGIN_Counter 000003d8 0 none ,g 2 __CommonCode@0 000003dc 0 none ,l 2 __CommonCode@1 000003e5 0 none ,l 2 FILE=obj\clk.obj 000003ef 0000049d af _CLK_Initialize 000003ef 0 none ,g 1 _CLK_Counter_Clear 00000404 0 none ,g 1 _CLK_Evaluate 00000408 0 none ,g 1 _CLK_Counter 0000049a 0 none ,g 1 FILE=obj\74hc.obj 0000049e 00000588 eb _IC_74HC166_Judge_State 0000049e 0 none ,g 1 _IC_74HC166_Out_QH 000004e0 0 none ,g 1 _IC74HC166_Initialize 00000557 0 none ,g 1 _IC74HC166_Counter_Clear 0000056b 0 none ,g 1 _IC74HC166_Counter 0000056f 0 none ,g 1 __CommonCode@0 00000573 0 none ,l 2 __CommonCode@1 0000057f 0 none ,l 2 SECTION=.RLIB FILE=memset 00000589 00000596 e _memset 00000589 0 none ,g 4 FILE=_COM_imul 00000597 000005a5 f __COM_imul 00000597 0 none ,g 1 FILE=_COM_ucdiv 000005a6 000005bd 18 __COM_ucdiv 000005a6 0 none ,g 1 FILE=_COM_ucrem 000005be 000005d2 15 __COM_ucrem 000005be 0 none ,g 2 FILE=_COM_uidiv 000005d3 000005ee 1c __COM_uidiv 000005d3 0 none ,g 2 SECTION=.bss FILE=obj\panel.obj 000ffce0 000ffce0 1 _I_04 000ffce0 0 none ,g 2 FILE=obj\digitalio.obj 000ffce2 000ffce4 3 _g_ucDGIN_LastRet 000ffce2 0 none ,g 2 _g_ucDGIN_ElapsedTime 000ffce3 0 none ,g 3 _g_ucDGIN_Count 000ffce4 0 none ,g 7 FILE=obj\clk.obj 000ffce6 000ffcea 5 _g_ucCLK_LastOut@1 000ffce6 0 none ,l 3 _g_ushCLK_ElapsedTime@2 000ffce8 0 none ,l 3 _g_ucCLK_Count@3 000ffcea 0 none ,l 5 FILE=obj\74hc.obj 000ffcec 000ffced 2 _g74HC166_LastCK 000ffcec 0 none ,g 3 _g74HC166_LastValue 000ffced 0 none ,g 4 SECTION=.dataR FILE=obj\panel.obj 000ffcee 000ffcfa d _F0303 000ffcee 0 none ,g 2 _F0500 000ffcef 0 none ,g 0 _F0501 000ffcf0 0 none ,g 0 _F0502 000ffcf1 0 none ,g 0 _F0505 000ffcf2 0 none ,g 0 _F0506 000ffcf3 0 none ,g 0 _F0507 000ffcf4 0 none ,g 0 _F0508 000ffcf5 0 none ,g 0 _F0509 000ffcf6 0 none ,g 0 _F0510 000ffcf7 0 none ,g 0 _F0511 000ffcf8 0 none ,g 0 _F0512 000ffcf9 0 none ,g 0 _F0600 000ffcfa 0 none ,g 2 FILE=obj\74hc.obj 000ffcfc 000ffcfc 1 _g74HC166_Count 000ffcfc 0 none ,g 7 SECTION=.stack_bss FILE=obj\cstart.obj 000ffcfe 000ffd3d 40 _stackend 000ffcfe 0 none ,l 0 _stacktop 000ffd3e 0 none ,l 1 SECTION=.sbss FILE=obj\common.obj 000ffe20 000ffe25 6 _fTx0Done 000ffe20 0 none ,g 0 _fTx6Done 000ffe21 0 none ,g 0 _fTm10ms 000ffe22 0 none ,g 3 _fTrg50ms 000ffe23 0 none ,g 2 _fTrg1s 000ffe24 0 none ,g 2 _fTrg10ms 000ffe25 0 none ,g 4 FILE=obj\timer.obj 000ffe26 000ffe28 3 _SysTm10ms 000ffe26 0 none ,g 3 _SysTm50ms 000ffe27 0 none ,g 3 _SysTm1s 000ffe28 0 none ,g 3 Absolute value symbols FILE=rlink_generates_03 __s.text 000000ce 0 none ,g 0 __e.text 00000589 0 none ,g 0 __s.textf 000000c4 0 none ,g 0 __e.textf 000000c4 0 none ,g 0 __s.const 00000080 0 none ,g 0 __e.const 00000080 0 none ,g 0 __s.constf 00000080 0 none ,g 0 __e.constf 00000080 0 none ,g 0 __s.data 00000082 0 none ,g 0 __e.data 00000091 0 none ,g 0 __s.sdata 00000080 0 none ,g 0 __e.sdata 00000080 0 none ,g 0 __s.bss 000ffce0 0 none ,g 0 __e.bss 000ffcee 0 none ,g 0 __s.sbss 000ffe20 0 none ,g 0 __e.sbss 000ffe29 0 none ,g 0 __s.dataR 000ffcee 0 none ,g 0 __e.dataR 000ffcfd 0 none ,g 0 __s.sdataR 000ffe2a 0 none ,g 0 __e.sdataR 000ffe2a 0 none ,g 0 __s.stack_bss 000ffcfe 0 none ,g 0 __e.stack_bss 000ffd3e 0 none ,g 0 __s.option_byte 000000c0 0 none ,g 0 __e.option_byte 000000c4 0 none ,g 0 __s.RLIB 00000589 0 none ,g 0 __e.RLIB 000005ef 0 none ,g 0 __s.vect 00000000 0 none ,g 0 __e.vect 00000080 0 none ,g 0 __s.security_id 000000c4 0 none ,g 0 __e.security_id 000000ce 0 none ,g 0 __RAM_ADDR_START 000ffce0 0 none ,g 0 __RAM_ADDR_END 000ffee0 0 none ,g 0 __STACK_ADDR_START 000ffe20 0 none ,g 0 __STACK_ADDR_END 000ffd3e 0 none ,g 0 *** Unfilled Areas *** AREA START END *** Delete Symbols *** SYMBOL SIZE INFO *** Variable Vector Table List *** ADDRESS SYMBOL/ADDRESS 00 _start 02 04 06 _MD_INTP0 08 _MD_INTP1 0a 0c 0e 10 12 _MD_INTTM00 14 16 18 1a _MD_INTP2 1c _MD_INTP3 1e 20 22 24 26 _MD_INTIT 28 2a 2c 2e 30 32 34 36 38 3a 3c 3e 40 42 44 46 48 4a 4c 4e 50 52 54 56 58 5a 5c 5e 60 62 64 66 68 6a 6c 6e 70 72 74 76 78 7a 7c 7e *** Cross Reference List *** No Unit Name Global.Symbol Location External Infomation ---- ----------- --------------- -------- --------------------- 0001 cstart SECTION=.text _start 000000ce _exit 0000010f 0001(00000110:.text) SECTION=.textf SECTION=.const SECTION=.constf SECTION=.data SECTION=.sdata SECTION=.bss SECTION=.sbss SECTION=.dataR SECTION=.sdataR SECTION=.stack_bss SECTION=.dataR SECTION=.sdataR 0002 opt_byte SECTION=.option_byte 0003 main SECTION=.text _main 00000111 0001(0000010c:.text) _main_loop 00000119 0003(00000118:.text) 0004 common SECTION=.text _MOV1_ 00000124 _NOT1_ 00000125 _WAIT 0000012c _BitMemGet 00000139 0012(00000398:.text) 0013(00000414:.text) 0014(000004bd:.text) _ByteMemGet 00000156 0012(000003a3:.text) 0014(00000586:.text) _BitMemSet 0000015e 0012(000003ec:.text) 0013(00000487:.text) 0014(000004d9:.text) _ByteMemSet 00000199 0012(00000367:.text) 0012(000003d1:.text) 0014(00000504:.text) 0014(0000057c:.text) _Port_Set 000001a2 0012(00000355:.text) _Port_Get 000001ce 0012(00000383:.text) SECTION=.sbss _fTx0Done 000ffe20 _fTx6Done 000ffe21 _fTm10ms 000ffe22 0005(000001f8:.text) 0005(00000232:.text) 0005(00000254:.text) _fTrg50ms 000ffe23 0005(0000022e:.text) 0005(00000245:.text) _fTrg1s 000ffe24 0005(00000230:.text) 0005(00000252:.text) _fTrg10ms 000ffe25 0005(0000022c:.text) 0005(00000237:.text) 0011(000002e7:.text) 0011(000002f7:.text) 0005 timer SECTION=.text _MD_INTTM00 000001eb _TM00_Init 000001fc 0010(000002c4:.text) _TM_10ms 0000022b 0003(00000120:.text) SECTION=.sbss _SysTm10ms 000ffe26 0005(000001ee:.text) 0005(000001f0:.text) 0005(000001f6:.text) _SysTm50ms 000ffe27 0005(0000023b:.text) 0005(0000023d:.text) 0005(00000243:.text) _SysTm1s 000ffe28 0005(00000248:.text) 0005(0000024a:.text) 0005(00000250:.text) 0006 int SECTION=.text _MD_INTP0 00000259 _MD_INTP1 0000025b _MD_INTP2 0000025d _MD_INTP3 0000025f _MD_INTIT 00000261 _INT_Init 00000263 0010(000002c1:.text) 0007 port SECTION=.text _PORT_Init 0000028e 0010(000002bb:.text) 0008 watchdogtimer SECTION=.text _WDT_Init 000002ab 0010(000002be:.text) _WDT_Reset 000002ac 0003(0000011d:.text) 0009 system SECTION=.text _Clock_Init 000002b0 0010(000002b8:.text) 0010 systeminit SECTION=.text _SystemInit 000002b1 0010(000002ca:.text) _hdwinit 000002c6 0001(000000d3:.text) 0003(00000112:.text) 0011 panel SECTION=.text _panel_init0 000002d0 0003(00000115:.text) _panel 000002dd 0003(0000011a:.text) SECTION=.bss _I_04 000ffce0 0011(000002f1:.text) 0011(00000318:.text) SECTION=.dataR _F0303 000ffcee 0011(00000303:.text) 0011(00000309:.text) _F0500 000ffcef _F0501 000ffcf0 _F0502 000ffcf1 _F0505 000ffcf2 _F0506 000ffcf3 _F0507 000ffcf4 _F0508 000ffcf5 _F0509 000ffcf6 _F0510 000ffcf7 _F0511 000ffcf8 _F0512 000ffcf9 _F0600 000ffcfa 0011(00000325:.text) 0011(0000032b:.text) SECTION=.data 0012 digitalio SECTION=.text _DGOUT_setValue 00000332 0011(00000330:.text) _DGIN_Initialize 00000357 0011(000002d2:.text) _DGIN_Counter_Clear 00000369 0011(000002de:.text) _DGIN_getValue 0000036d 0011(000002ec:.text) _DGIN_Counter 000003d8 0011(000002d5:.text) 0011(000002f4:.text) SECTION=.bss _g_ucDGIN_LastRet 000ffce2 0012(00000395:.text) 0012(000003e9:.text) _g_ucDGIN_ElapsedTime 000ffce3 0012(00000364:.text) 0012(000003a0:.text) 0012(000003ce:.text) _g_ucDGIN_Count 000ffce4 0012(00000360:.text) 0012(0000036a:.text) 0012(00000392:.text) 0012(0000039d:.text) 0012(000003cb:.text) 0012(000003d9:.text) 0012(000003e6:.text) 0013 clk SECTION=.text _CLK_Initialize 000003ef 0011(000002d8:.text) _CLK_Counter_Clear 00000404 0011(000002e1:.text) _CLK_Evaluate 00000408 0011(000002fe:.text) _CLK_Counter 0000049a 0011(00000306:.text) SECTION=.bss 0014 74hc SECTION=.text _IC_74HC166_Judge_State 0000049e 0011(0000030f:.text) _IC_74HC166_Out_QH 000004e0 0011(00000320:.text) _IC74HC166_Initialize 00000557 0011(000002db:.text) _IC74HC166_Counter_Clear 0000056b 0011(000002e4:.text) _IC74HC166_Counter 0000056f 0011(00000328:.text) SECTION=.bss _g74HC166_LastCK 000ffcec 0014(000004ba:.text) 0014(000004d6:.text) 0014(0000055b:.text) _g74HC166_LastValue 000ffced 0014(00000501:.text) 0014(00000565:.text) 0014(00000579:.text) 0014(00000583:.text) SECTION=.dataR _g74HC166_Count 000ffcfc 0014(000004b7:.text) 0014(000004d3:.text) 0014(000004fd:.text) 0014(0000056c:.text) 0014(00000570:.text) 0014(00000576:.text) 0014(00000580:.text) SECTION=.data 0015 memset SECTION=.RLIB _memset 00000589 0013(000003f6:.text) 0013(00000401:.text) 0014(0000055e:.text) 0014(00000568:.text) SECTION=.text 0016 _COM_imul SECTION=.RLIB __COM_imul 00000597 0013(00000431:.text) SECTION=.text 0017 _COM_ucdiv SECTION=.RLIB __COM_ucdiv 000005a6 0012(000003df:.text) SECTION=.text 0018 _COM_ucrem SECTION=.RLIB __COM_ucrem 000005be 0012(0000034a:.text) 0012(0000037c:.text) SECTION=.text 0019 _COM_uidiv SECTION=.RLIB __COM_uidiv 000005d3 0013(0000043c:.text) 0013(00000450:.text) SECTION=.text 0020 rlink_generates_01 SECTION=.vect 0021 rlink_generates_02 SECTION=.security_id 0022 rlink_generates_03 SECTION= __s.vect 00000000 __s.const 00000080 __e.const 00000080 __s.constf 00000080 __e.constf 00000080 __s.sdata 00000080 __e.sdata 00000080 __e.vect 00000080 __s.data 00000082 __e.data 00000091 __s.option_byte 000000c0 __s.textf 000000c4 __e.textf 000000c4 __e.option_byte 000000c4 __s.security_id 000000c4 __s.text 000000ce __e.security_id 000000ce __e.text 00000589 __s.RLIB 00000589 __e.RLIB 000005ef __s.bss 000ffce0 __RAM_ADDR_START 000ffce0 __e.bss 000ffcee __s.dataR 000ffcee __e.dataR 000ffcfd __s.stack_bss 000ffcfe __e.stack_bss 000ffd3e __STACK_ADDR_END 000ffd3e __s.sbss 000ffe20 __STACK_ADDR_START 000ffe20 __e.sbss 000ffe29 __s.sdataR 000ffe2a __e.sdataR 000ffe2a __RAM_ADDR_END 000ffee0
Renesas Optimizing Linker (W2.04.00 ) 14-May-2017 07:18:01 *** Options *** -subcommand=DefaultBuild\EZPLforRL78v2andCCRLv102.clnk -Input=DefaultBuild\cstart.obj -Input=DefaultBuild\opt_byte.obj -Input=DefaultBuild\main.obj -Input=DefaultBuild\common.obj -Input=DefaultBuild\timer.obj -Input=DefaultBuild\int.obj -Input=DefaultBuild\port.obj -Input=DefaultBuild\watchdogtimer.obj -Input=DefaultBuild\system.obj -Input=DefaultBuild\systeminit.obj -Input=DefaultBuild\panel.obj -Input=DefaultBuild\digitalio.obj -Input=DefaultBuild\clk.obj -Input=DefaultBuild\74hc.obj -SECURITY_ID=00000000000000000000 -DEVICE=E:\tools\micom\Renesas\CS+\CC\Device\RL78\Devicefile\DR5F10Y47.DVF -DEBug -NOCOmpress -OUtput=DefaultBuild\EZPLforRL78v2andCCRLv102.abs -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4s.lib -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4r.lib -ENTry=_start -LISt=DefaultBuild\EZPLforRL78v2andCCRLv102.map -SHow=ALL -AUTO_SECTION_LAYOUT -STARt=.text,.textf,.SLIB,.RLIB/000CE -ROm=.data=.dataR -ROm=.sdata=.sdataR -NOMessage -NOLOgo -end *** Error information *** *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .text 000000ce 0000054e 481 1 .textf 0000054f 0000054f 0 1 .SLIB 0000054f 0000054f 0 1 .RLIB 0000054f 000005b4 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 000004e7 Byte(s) *** Symbol List *** SECTION= FILE= START END SIZE SYMBOL ADDR SIZE INFO COUNTS OPT SECTION=.vect FILE=rlink_generates_01 00000000 0000007f 80 SECTION=.data FILE=DefaultBuild\main.obj 00000082 00000085 4 SECTION=.option_byte FILE=DefaultBuild\opt_byte.obj 000000c0 000000c3 4 SECTION=.security_id FILE=rlink_generates_02 000000c4 000000cd a SECTION=.text FILE=DefaultBuild\cstart.obj 000000ce 0000010f 42 _start 000000ce 0 entry,g 0 _exit 0000010e 0 none ,g 1 FILE=DefaultBuild\main.obj 00000110 0000054e 43f _main 00000110 6 func ,g 1 ch _main_loop 00000116 b func ,g 1 _hdwinit 00000121 a func ,g 2 _panel_init0 0000012b d func ,g 1 _panel 00000138 55 func ,g 1 _TM_10ms 0000018d 2e func ,g 1 _BitMemGet 000001bb 1d func ,g 3 _ByteMemGet 000001d8 8 func ,g 2 _BitMemSet 000001e0 3b func ,g 3 _ByteMemSet 0000021b 9 func ,g 4 _Port_Set 00000224 2c func ,g 1 _Port_Get 00000250 1d func ,g 1 _MD_INTTM00 0000026d 11 func ,g 0 _TM00_Init 0000027e 2f func ,g 1 _MD_INTP0 000002ad 2 func ,g 0 _MD_INTP1 000002af 2 func ,g 0 _MD_INTP2 000002b1 2 func ,g 0 _MD_INTP3 000002b3 2 func ,g 0 _MD_INTIT 000002b5 2 func ,g 0 _INT_Init 000002b7 2b func ,g 1 _PORT_Init 000002e2 1d func ,g 1 _SystemInit 000002ff f func ,g 1 _DGIN_Initialize 0000030e 12 func ,g 1 _DGIN_Counter 00000320 4 func ,g 2 _CLK_Initialize 00000324 13 func ,g 1 ch _IC74HC166_Initialize 00000337 12 func ,g 1 ch _DGIN_getValue 00000349 6a func ,g 1 ch _CLK_Evaluate 000003b3 8f func ,g 1 ch _CLK_Counter 00000442 4 func ,g 1 _IC_74HC166_Judge_State 00000446 42 func ,g 1 _IC_74HC166_Out_QH 00000488 77 func ,g 1 _IC74HC166_Counter 000004ff 4 func ,g 1 _DGOUT_setValue 00000503 24 func ,g 1 ch __CommonCode@0 00000527 a func ,l 2 __CommonCode@1 00000531 8 func ,l 2 ch __CommonCode@2 00000539 c func ,l 2 __CommonCode@3 00000545 a func ,l 2 SECTION=.RLIB FILE=memset 0000054f 0000055c e _memset 0000054f 0 none ,g 4 FILE=_COM_imul 0000055d 0000056b f __COM_imul 0000055d 0 none ,g 1 FILE=_COM_ucdiv 0000056c 00000583 18 __COM_ucdiv 0000056c 0 none ,g 1 FILE=_COM_ucrem 00000584 00000598 15 __COM_ucrem 00000584 0 none ,g 2 FILE=_COM_uidiv 00000599 000005b4 1c __COM_uidiv 00000599 0 none ,g 2 SECTION=.bss FILE=DefaultBuild\main.obj 000ffce0 000ffcea b _I_04 000ffce0 1 data ,g 2 _g_ucDGIN_LastRet 000ffce1 1 data ,g 2 _g_ucDGIN_ElapsedTime 000ffce2 1 data ,g 3 _g_ucDGIN_Count 000ffce3 1 data ,g 7 _g_ucCLK_LastOut@1 000ffce4 1 data ,l 3 _g_ushCLK_ElapsedTime@2 000ffce6 2 data ,l 3 _g_ucCLK_Count@3 000ffce8 1 data ,l 5 _g74HC166_LastCK 000ffce9 1 data ,g 3 _g74HC166_LastValue 000ffcea 1 data ,g 4 SECTION=.dataR FILE=DefaultBuild\main.obj 000ffcec 000ffcef 4 _F0303 000ffcec 1 data ,g 2 _F0512 000ffced 1 data ,g 0 _F0600 000ffcee 1 data ,g 2 _g74HC166_Count 000ffcef 1 data ,g 7 SECTION=.sbss FILE=DefaultBuild\main.obj 000ffe20 000ffe26 7 _fTm10ms 000ffe20 1 data ,g 3 _fTrg50ms 000ffe21 1 data ,g 2 _fTrg1s 000ffe22 1 data ,g 2 _fTrg10ms 000ffe23 1 data ,g 4 _SysTm10ms 000ffe24 1 data ,g 3 _SysTm50ms 000ffe25 1 data ,g 3 _SysTm1s 000ffe26 1 data ,g 3 Absolute value symbols FILE=rlink_generates_03 __s.text 000000ce 0 none ,g 0 __e.text 0000054f 0 none ,g 0 __s.textf 0000054f 0 none ,g 0 __e.textf 0000054f 0 none ,g 0 __s.const 00000080 0 none ,g 0 __e.const 00000080 0 none ,g 0 __s.constf 00000080 0 none ,g 0 __e.constf 00000080 0 none ,g 0 __s.data 00000082 0 none ,g 0 __e.data 00000086 0 none ,g 0 __s.sdata 00000080 0 none ,g 0 __e.sdata 00000080 0 none ,g 0 __s.bss 000ffce0 0 none ,g 0 __e.bss 000ffceb 0 none ,g 0 __s.sbss 000ffe20 0 none ,g 0 __e.sbss 000ffe27 0 none ,g 0 __s.dataR 000ffcec 0 none ,g 0 __e.dataR 000ffcf0 0 none ,g 0 __s.sdataR 000ffe28 0 none ,g 0 __e.sdataR 000ffe28 0 none ,g 0 __s.RLIB 0000054f 0 none ,g 0 __e.RLIB 000005b5 0 none ,g 0 __s.SLIB 0000054f 0 none ,g 0 __e.SLIB 0000054f 0 none ,g 0 __s.option_byte 000000c0 0 none ,g 0 __e.option_byte 000000c4 0 none ,g 0 __s.vect 00000000 0 none ,g 0 __e.vect 00000080 0 none ,g 0 __s.security_id 000000c4 0 none ,g 0 __e.security_id 000000ce 0 none ,g 0 __RAM_ADDR_START 000ffce0 0 none ,g 1 __RAM_ADDR_END 000ffee0 0 none ,g 1 __STACK_ADDR_START 000ffe20 0 none ,g 1 __STACK_ADDR_END 000ffcfa 0 none ,g 0 *** Unfilled Areas *** AREA START END *** Delete Symbols *** SYMBOL SIZE INFO _WDT_Reset 4 func ,g _MOV1_ 1 func ,g _NOT1_ 7 func ,g _WAIT d func ,g _WDT_Init 1 func ,g _Clock_Init 1 func ,g _DGIN_Counter_Clear 4 func ,g _CLK_Counter_Clear 4 func ,g _IC74HC166_Counter_Clear 4 func ,g _fTx0Done 1 data ,g _fTx6Done 1 data ,g _F0500 1 data ,g _F0501 1 data ,g _F0502 1 data ,g _F0505 1 data ,g _F0506 1 data ,g _F0507 1 data ,g _F0508 1 data ,g _F0509 1 data ,g _F0510 1 data ,g _F0511 1 data ,g *** Variable Vector Table List *** ADDRESS SYMBOL/ADDRESS 00 _start 02 04 06 _MD_INTP0 08 _MD_INTP1 0a 0c 0e 10 12 _MD_INTTM00 14 16 18 1a _MD_INTP2 1c _MD_INTP3 1e 20 22 24 26 _MD_INTIT 28 2a 2c 2e 30 32 34 36 38 3a 3c 3e 40 42 44 46 48 4a 4c 4e 50 52 54 56 58 5a 5c 5e 60 62 64 66 68 6a 6c 6e 70 72 74 76 78 7a 7c 7e *** Cross Reference List *** No Unit Name Global.Symbol Location External Infomation ---- ----------- --------------- -------- --------------------- 0001 cstart SECTION=.text _start 000000ce _exit 0000010e 0001(0000010f:.text) SECTION=.textf SECTION=.const SECTION=.constf SECTION=.data SECTION=.sdata SECTION=.bss SECTION=.sbss SECTION=.dataR SECTION=.sdataR SECTION=.RLIB SECTION=.SLIB SECTION=.dataR SECTION=.sdataR 0002 opt_byte SECTION=.option_byte 0003 main SECTION=.sbss _fTm10ms 000ffe20 0003(00000194:.text) 0003(000001b6:.text) 0003(0000027a:.text) _fTrg50ms 000ffe21 0003(00000190:.text) 0003(000001a7:.text) _fTrg1s 000ffe22 0003(00000192:.text) 0003(000001b4:.text) _fTrg10ms 000ffe23 0003(00000142:.text) 0003(00000152:.text) 0003(0000018e:.text) 0003(00000199:.text) _SysTm10ms 000ffe24 0003(00000270:.text) 0003(00000272:.text) 0003(00000278:.text) _SysTm50ms 000ffe25 0003(0000019d:.text) 0003(0000019f:.text) 0003(000001a5:.text) _SysTm1s 000ffe26 0003(000001aa:.text) 0003(000001ac:.text) 0003(000001b2:.text) SECTION=.text _main 00000110 0001(0000010b:.text) _main_loop 00000116 _hdwinit 00000121 0001(000000d3:.text) 0003(00000111:.text) _panel_init0 0000012b 0003(00000114:.text) _panel 00000138 0003(00000117:.text) _TM_10ms 0000018d 0003(0000011d:.text) _BitMemGet 000001bb 0003(00000373:.text) 0003(000003bf:.text) 0003(00000465:.text) _ByteMemGet 000001d8 0003(0000037e:.text) 0003(0000054c:.text) _BitMemSet 000001e0 0003(0000042f:.text) 0003(00000481:.text) 0003(0000052e:.text) _ByteMemSet 0000021b 0003(0000031e:.text) 0003(000003ac:.text) 0003(000004ac:.text) 0003(00000542:.text) _Port_Set 00000224 0003(00000525:.text) _Port_Get 00000250 0003(0000035e:.text) _MD_INTTM00 0000026d _TM00_Init 0000027e 0003(0000030c:.text) _MD_INTP0 000002ad _MD_INTP1 000002af _MD_INTP2 000002b1 _MD_INTP3 000002b3 _MD_INTIT 000002b5 _INT_Init 000002b7 0003(00000309:.text) _PORT_Init 000002e2 0003(00000306:.text) _SystemInit 000002ff 0003(00000125:.text) _DGIN_Initialize 0000030e 0003(0000012d:.text) _DGIN_Counter 00000320 0003(00000130:.text) 0003(0000014f:.text) _CLK_Initialize 00000324 0003(00000133:.text) _IC74HC166_Initialize 00000337 0003(00000136:.text) _DGIN_getValue 00000349 0003(00000147:.text) _CLK_Evaluate 000003b3 0003(00000159:.text) _CLK_Counter 00000442 0003(00000161:.text) _IC_74HC166_Judge_State 00000446 0003(0000016a:.text) _IC_74HC166_Out_QH 00000488 0003(0000017b:.text) _IC74HC166_Counter 000004ff 0003(00000183:.text) _DGOUT_setValue 00000503 0003(0000018b:.text) SECTION=.bss _I_04 000ffce0 0003(0000014c:.text) 0003(00000173:.text) _g_ucDGIN_LastRet 000ffce1 0003(00000370:.text) 0003(0000052b:.text) _g_ucDGIN_ElapsedTime 000ffce2 0003(0000031b:.text) 0003(0000037b:.text) 0003(000003a9:.text) _g_ucDGIN_Count 000ffce3 0003(00000139:.text) 0003(00000317:.text) 0003(00000321:.text) 0003(0000036d:.text) 0003(00000378:.text) 0003(000003a6:.text) 0003(00000528:.text) _g74HC166_LastCK 000ffce9 0003(0000033b:.text) 0003(00000462:.text) 0003(0000047e:.text) _g74HC166_LastValue 000ffcea 0003(00000344:.text) 0003(000004a9:.text) 0003(0000053f:.text) 0003(00000549:.text) SECTION=.dataR _F0303 000ffcec 0003(0000015e:.text) 0003(00000164:.text) _F0512 000ffced _F0600 000ffcee 0003(00000180:.text) 0003(00000186:.text) _g74HC166_Count 000ffcef 0003(0000013f:.text) 0003(0000045f:.text) 0003(0000047b:.text) 0003(000004a5:.text) 0003(00000500:.text) 0003(0000053c:.text) 0003(00000546:.text) SECTION=.data 0004 common 0005 timer 0006 int 0007 port 0008 watchdogtimer 0009 system 0010 systeminit 0011 panel 0012 digitalio 0013 clk 0014 74hc 0015 memset SECTION=.RLIB _memset 0000054f 0003(0000032b:.text) 0003(00000335:.text) 0003(0000033e:.text) 0003(00000347:.text) SECTION=.text 0016 _COM_imul SECTION=.RLIB __COM_imul 0000055d 0003(000003dc:.text) SECTION=.text 0017 _COM_ucdiv SECTION=.RLIB __COM_ucdiv 0000056c 0003(00000534:.text) SECTION=.text 0018 _COM_ucrem SECTION=.RLIB __COM_ucrem 00000584 0003(00000358:.text) 0003(0000051b:.text) SECTION=.text 0019 _COM_uidiv SECTION=.RLIB __COM_uidiv 00000599 0003(000003e6:.text) 0003(000003f9:.text) SECTION=.text 0020 rlink_generates_01 SECTION=.vect 0021 rlink_generates_02 SECTION=.security_id 0022 rlink_generates_03 SECTION= __s.vect 00000000 __s.const 00000080 __e.const 00000080 __s.constf 00000080 __e.constf 00000080 __s.sdata 00000080 __e.sdata 00000080 __e.vect 00000080 __s.data 00000082 __e.data 00000086 __s.option_byte 000000c0 __e.option_byte 000000c4 __s.security_id 000000c4 __s.text 000000ce __e.security_id 000000ce __e.text 0000054f __s.textf 0000054f __e.textf 0000054f __s.RLIB 0000054f __s.SLIB 0000054f __e.SLIB 0000054f __e.RLIB 000005b5 __s.bss 000ffce0 __RAM_ADDR_START 000ffce0 0001(000000d6:.text) __e.bss 000ffceb __s.dataR 000ffcec __e.dataR 000ffcf0 __STACK_ADDR_END 000ffcfa __s.sbss 000ffe20 __STACK_ADDR_START 000ffe20 0001(000000d0:.text) __e.sbss 000ffe27 __s.sdataR 000ffe28 __e.sdataR 000ffe28 __RAM_ADDR_END 000ffee0 0001(000000d9:.text)
*** Mapping List ***
SECTION START END SIZE ALIGN
.vect 00000000 0000007f 80 0
.const 00000080 00000080 0 2
.constf 00000080 00000080 0 2
.sdata 00000080 00000080 0 2
.data 00000082 00000085 4 2
.option_byte 000000c0 000000c3 4 1
.security_id 000000c4 000000cd a 1
.text 000000ce 0000054e 481 1
.textf 0000054f 0000054f 0 1
.SLIB 0000054f 0000054f 0 1
.RLIB 0000054f 000005b4 66 1
.bss 000ffce0 000ffcea b 2
.dataR 000ffcec 000ffcef 4 2
.sbss 000ffe20 000ffe26 7 2
.sdataR 000ffe28 000ffe28 0 2
*** Total Section Size ***
RAMDATA SECTION: 00000016 Byte(s)
ROMDATA SECTION: 00000092 Byte(s)
PROGRAM SECTION: 000004e7 Byte(s)
...
_WDT_Reset 4 func ,g
_MOV1_ 1 func ,g
_NOT1_ 7 func ,g
_WAIT d func ,g
_WDT_Init 1 func ,g
_Clock_Init 1 func ,g
_DGIN_Counter_Clear 4 func ,g
_CLK_Counter_Clear 4 func ,g
_IC74HC166_Counter_Clear 4 func ,g
_fTx0Done 1 data ,g
_fTx6Done 1 data ,g
Renesas Optimizing Linker (W2.04.00 ) 14-May-2017 07:24:07 *** Options *** -subcommand=DefaultBuild\EZPLforRL78v2andCCRLv102.clnk -Input=DefaultBuild\opt_byte.obj -Input=DefaultBuild\main.obj -Input=DefaultBuild\cstart.obj -Input=DefaultBuild\common.obj -Input=DefaultBuild\timer.obj -Input=DefaultBuild\int.obj -Input=DefaultBuild\port.obj -Input=DefaultBuild\watchdogtimer.obj -Input=DefaultBuild\system.obj -Input=DefaultBuild\systeminit.obj -Input=DefaultBuild\panel.obj -Input=DefaultBuild\digitalio.obj -Input=DefaultBuild\clk.obj -Input=DefaultBuild\74hc.obj -SECURITY_ID=00000000000000000000 -DEVICE=E:\tools\micom\Renesas\CS+\CC\Device\RL78\Devicefile\DR5F10Y47.DVF -DEBug -NOCOmpress -OUtput=DefaultBuild\EZPLforRL78v2andCCRLv102.abs -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4s.lib -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4r.lib -ENTry=_start -LISt=DefaultBuild\EZPLforRL78v2andCCRLv102.map -SHow=ALL -AUTO_SECTION_LAYOUT -STARt=.text,.textf,.SLIB,.RLIB/000CE -ROm=.data=.dataR -ROm=.sdata=.sdataR -NOMessage -NOLOgo -end *** Error information *** *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .text 000000ce 00000581 4b4 1 .textf 00000582 00000582 0 1 .SLIB 00000582 00000582 0 1 .RLIB 00000582 000005e7 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 0000051a Byte(s) *** Symbol List *** SECTION= FILE= START END SIZE SYMBOL ADDR SIZE INFO COUNTS OPT SECTION=.vect FILE=rlink_generates_01 00000000 0000007f 80 SECTION=.data FILE=DefaultBuild\main.obj 00000082 00000085 4 SECTION=.option_byte FILE=DefaultBuild\opt_byte.obj 000000c0 000000c3 4 SECTION=.security_id FILE=rlink_generates_02 000000c4 000000cd a SECTION=.text FILE=DefaultBuild\main.obj 000000ce 0000053f 472 _main 000000ce 8 func ,g 1 _main_loop 000000d6 b func ,g 1 _hdwinit 000000e1 a func ,g 2 _panel_init0 000000eb d func ,g 1 _panel 000000f8 55 func ,g 1 _WDT_Reset 0000014d 4 func ,g 0 _TM_10ms 00000151 2e func ,g 1 _MOV1_ 0000017f 1 func ,g 0 _NOT1_ 00000180 7 func ,g 0 _WAIT 00000187 d func ,g 0 _BitMemGet 00000194 1d func ,g 3 _ByteMemGet 000001b1 8 func ,g 2 _BitMemSet 000001b9 3b func ,g 3 _ByteMemSet 000001f4 9 func ,g 4 _Port_Set 000001fd 2c func ,g 1 _Port_Get 00000229 1d func ,g 1 _MD_INTTM00 00000246 11 func ,g 0 _TM00_Init 00000257 2f func ,g 1 _MD_INTP0 00000286 2 func ,g 0 _MD_INTP1 00000288 2 func ,g 0 _MD_INTP2 0000028a 2 func ,g 0 _MD_INTP3 0000028c 2 func ,g 0 _MD_INTIT 0000028e 2 func ,g 0 _INT_Init 00000290 2b func ,g 1 _PORT_Init 000002bb 1d func ,g 1 _WDT_Init 000002d8 1 func ,g 0 _Clock_Init 000002d9 1 func ,g 0 _SystemInit 000002da f func ,g 1 _DGIN_Initialize 000002e9 12 func ,g 1 _DGIN_Counter 000002fb 4 func ,g 2 _CLK_Initialize 000002ff 15 func ,g 1 _IC74HC166_Initialize 00000314 14 func ,g 1 _DGIN_Counter_Clear 00000328 4 func ,g 0 _CLK_Counter_Clear 0000032c 4 func ,g 0 _IC74HC166_Counter_Clear 00000330 4 func ,g 0 _DGIN_getValue 00000334 6b func ,g 1 _CLK_Evaluate 0000039f 92 func ,g 1 _CLK_Counter 00000431 4 func ,g 1 _IC_74HC166_Judge_State 00000435 42 func ,g 1 _IC_74HC166_Out_QH 00000477 77 func ,g 1 _IC74HC166_Counter 000004ee 4 func ,g 1 _DGOUT_setValue 000004f2 25 func ,g 1 __CommonCode@0 00000517 a func ,l 2 __CommonCode@1 00000521 9 func ,l 2 __CommonCode@2 0000052a c func ,l 2 __CommonCode@3 00000536 a func ,l 2 FILE=DefaultBuild\cstart.obj 00000540 00000581 42 _start 00000540 0 entry,g 0 _exit 00000580 0 none ,g 1 SECTION=.RLIB FILE=memset 00000582 0000058f e _memset 00000582 0 none ,g 4 FILE=_COM_imul 00000590 0000059e f __COM_imul 00000590 0 none ,g 1 FILE=_COM_ucdiv 0000059f 000005b6 18 __COM_ucdiv 0000059f 0 none ,g 1 FILE=_COM_ucrem 000005b7 000005cb 15 __COM_ucrem 000005b7 0 none ,g 2 FILE=_COM_uidiv 000005cc 000005e7 1c __COM_uidiv 000005cc 0 none ,g 2 SECTION=.bss FILE=DefaultBuild\main.obj 000ffce0 000ffcea b _I_04 000ffce0 1 data ,g 2 _g_ucDGIN_LastRet 000ffce1 1 data ,g 2 _g_ucDGIN_ElapsedTime 000ffce2 1 data ,g 3 _g_ucDGIN_Count 000ffce3 1 data ,g 8 _g_ucCLK_LastOut@1 000ffce4 1 data ,l 3 _g_ushCLK_ElapsedTime@2 000ffce6 2 data ,l 3 _g_ucCLK_Count@3 000ffce8 1 data ,l 6 _g74HC166_LastCK 000ffce9 1 data ,g 3 _g74HC166_LastValue 000ffcea 1 data ,g 4 SECTION=.dataR FILE=DefaultBuild\main.obj 000ffcec 000ffcef 4 _F0303 000ffcec 1 data ,g 2 _F0512 000ffced 1 data ,g 0 _F0600 000ffcee 1 data ,g 2 _g74HC166_Count 000ffcef 1 data ,g 8 SECTION=.sbss FILE=DefaultBuild\main.obj 000ffe20 000ffe26 7 _fTm10ms 000ffe20 1 data ,g 3 _fTrg50ms 000ffe21 1 data ,g 2 _fTrg1s 000ffe22 1 data ,g 2 _fTrg10ms 000ffe23 1 data ,g 4 _SysTm10ms 000ffe24 1 data ,g 3 _SysTm50ms 000ffe25 1 data ,g 3 _SysTm1s 000ffe26 1 data ,g 3 Absolute value symbols FILE=rlink_generates_03 __s.option_byte 000000c0 0 none ,g 0 __e.option_byte 000000c4 0 none ,g 0 __s.text 000000ce 0 none ,g 0 __e.text 00000582 0 none ,g 0 __s.data 00000082 0 none ,g 0 __e.data 00000086 0 none ,g 0 __s.bss 000ffce0 0 none ,g 0 __e.bss 000ffceb 0 none ,g 0 __s.sbss 000ffe20 0 none ,g 0 __e.sbss 000ffe27 0 none ,g 0 __s.textf 00000582 0 none ,g 0 __e.textf 00000582 0 none ,g 0 __s.const 00000080 0 none ,g 0 __e.const 00000080 0 none ,g 0 __s.constf 00000080 0 none ,g 0 __e.constf 00000080 0 none ,g 0 __s.sdata 00000080 0 none ,g 0 __e.sdata 00000080 0 none ,g 0 __s.dataR 000ffcec 0 none ,g 0 __e.dataR 000ffcf0 0 none ,g 0 __s.sdataR 000ffe28 0 none ,g 0 __e.sdataR 000ffe28 0 none ,g 0 __s.RLIB 00000582 0 none ,g 0 __e.RLIB 000005e8 0 none ,g 0 __s.SLIB 00000582 0 none ,g 0 __e.SLIB 00000582 0 none ,g 0 __s.vect 00000000 0 none ,g 0 __e.vect 00000080 0 none ,g 0 __s.security_id 000000c4 0 none ,g 0 __e.security_id 000000ce 0 none ,g 0 __RAM_ADDR_START 000ffce0 0 none ,g 1 __RAM_ADDR_END 000ffee0 0 none ,g 1 __STACK_ADDR_START 000ffe20 0 none ,g 1 __STACK_ADDR_END 000ffcfa 0 none ,g 0 *** Unfilled Areas *** AREA START END *** Delete Symbols *** SYMBOL SIZE INFO _fTx0Done 1 data ,g _fTx6Done 1 data ,g _F0500 1 data ,g _F0501 1 data ,g _F0502 1 data ,g _F0505 1 data ,g _F0506 1 data ,g _F0507 1 data ,g _F0508 1 data ,g _F0509 1 data ,g _F0510 1 data ,g _F0511 1 data ,g *** Variable Vector Table List *** ADDRESS SYMBOL/ADDRESS 00 _start 02 04 06 _MD_INTP0 08 _MD_INTP1 0a 0c 0e 10 12 _MD_INTTM00 14 16 18 1a _MD_INTP2 1c _MD_INTP3 1e 20 22 24 26 _MD_INTIT 28 2a 2c 2e 30 32 34 36 38 3a 3c 3e 40 42 44 46 48 4a 4c 4e 50 52 54 56 58 5a 5c 5e 60 62 64 66 68 6a 6c 6e 70 72 74 76 78 7a 7c 7e *** Cross Reference List *** No Unit Name Global.Symbol Location External Infomation ---- ----------- --------------- -------- --------------------- 0001 opt_byte SECTION=.option_byte 0002 main SECTION=.sbss _fTm10ms 000ffe20 0002(00000158:.text) 0002(0000017a:.text) 0002(00000253:.text) _fTrg50ms 000ffe21 0002(00000154:.text) 0002(0000016b:.text) _fTrg1s 000ffe22 0002(00000156:.text) 0002(00000178:.text) _fTrg10ms 000ffe23 0002(00000102:.text) 0002(00000112:.text) 0002(00000152:.text) 0002(0000015d:.text) _SysTm10ms 000ffe24 0002(00000249:.text) 0002(0000024b:.text) 0002(00000251:.text) _SysTm50ms 000ffe25 0002(00000161:.text) 0002(00000163:.text) 0002(00000169:.text) _SysTm1s 000ffe26 0002(0000016e:.text) 0002(00000170:.text) 0002(00000176:.text) SECTION=.text _main 000000ce 0003(0000057d:.text) _main_loop 000000d6 0002(000000d5:.text) _hdwinit 000000e1 0002(000000cf:.text) 0003(00000545:.text) _panel_init0 000000eb 0002(000000d2:.text) _panel 000000f8 0002(000000d7:.text) _WDT_Reset 0000014d _TM_10ms 00000151 0002(000000dd:.text) _MOV1_ 0000017f _NOT1_ 00000180 _WAIT 00000187 _BitMemGet 00000194 0002(0000035f:.text) 0002(000003ab:.text) 0002(00000454:.text) _ByteMemGet 000001b1 0002(0000036a:.text) 0002(0000053d:.text) _BitMemSet 000001b9 0002(0000041e:.text) 0002(00000470:.text) 0002(0000051e:.text) _ByteMemSet 000001f4 0002(000002f9:.text) 0002(00000398:.text) 0002(0000049b:.text) 0002(00000533:.text) _Port_Set 000001fd 0002(00000515:.text) _Port_Get 00000229 0002(0000034a:.text) _MD_INTTM00 00000246 _TM00_Init 00000257 0002(000002e7:.text) _MD_INTP0 00000286 _MD_INTP1 00000288 _MD_INTP2 0000028a _MD_INTP3 0000028c _MD_INTIT 0000028e _INT_Init 00000290 0002(000002e4:.text) _PORT_Init 000002bb 0002(000002e1:.text) _WDT_Init 000002d8 _Clock_Init 000002d9 _SystemInit 000002da 0002(000000e5:.text) _DGIN_Initialize 000002e9 0002(000000ed:.text) _DGIN_Counter 000002fb 0002(000000f0:.text) 0002(0000010f:.text) _CLK_Initialize 000002ff 0002(000000f3:.text) _IC74HC166_Initialize 00000314 0002(000000f6:.text) _DGIN_Counter_Clear 00000328 _CLK_Counter_Clear 0000032c _IC74HC166_Counter_Clear 00000330 _DGIN_getValue 00000334 0002(00000107:.text) _CLK_Evaluate 0000039f 0002(00000119:.text) _CLK_Counter 00000431 0002(00000121:.text) _IC_74HC166_Judge_State 00000435 0002(0000012a:.text) _IC_74HC166_Out_QH 00000477 0002(0000013b:.text) _IC74HC166_Counter 000004ee 0002(00000143:.text) _DGOUT_setValue 000004f2 0002(0000014b:.text) SECTION=.bss _I_04 000ffce0 0002(0000010c:.text) 0002(00000133:.text) _g_ucDGIN_LastRet 000ffce1 0002(0000035c:.text) 0002(0000051b:.text) _g_ucDGIN_ElapsedTime 000ffce2 0002(000002f6:.text) 0002(00000367:.text) 0002(00000395:.text) _g_ucDGIN_Count 000ffce3 0002(000000f9:.text) 0002(000002f2:.text) 0002(000002fc:.text) 0002(00000329:.text) 0002(00000359:.text) 0002(00000364:.text) 0002(00000392:.text) 0002(00000518:.text) _g74HC166_LastCK 000ffce9 0002(00000318:.text) 0002(00000451:.text) 0002(0000046d:.text) _g74HC166_LastValue 000ffcea 0002(00000322:.text) 0002(00000498:.text) 0002(00000530:.text) 0002(0000053a:.text) SECTION=.dataR _F0303 000ffcec 0002(0000011e:.text) 0002(00000124:.text) _F0512 000ffced _F0600 000ffcee 0002(00000140:.text) 0002(00000146:.text) _g74HC166_Count 000ffcef 0002(000000ff:.text) 0002(00000331:.text) 0002(0000044e:.text) 0002(0000046a:.text) 0002(00000494:.text) 0002(000004ef:.text) 0002(0000052d:.text) 0002(00000537:.text) SECTION=.data 0003 cstart SECTION=.text _start 00000540 _exit 00000580 0003(00000581:.text) SECTION=.textf SECTION=.const SECTION=.constf SECTION=.data SECTION=.sdata SECTION=.bss SECTION=.sbss SECTION=.dataR SECTION=.sdataR SECTION=.RLIB SECTION=.SLIB SECTION=.dataR SECTION=.sdataR 0004 common 0005 timer 0006 int 0007 port 0008 watchdogtimer 0009 system 0010 systeminit 0011 panel 0012 digitalio 0013 clk 0014 74hc 0015 memset SECTION=.RLIB _memset 00000582 0002(00000306:.text) 0002(00000311:.text) 0002(0000031b:.text) 0002(00000325:.text) SECTION=.text 0016 _COM_imul SECTION=.RLIB __COM_imul 00000590 0002(000003c8:.text) SECTION=.text 0017 _COM_ucdiv SECTION=.RLIB __COM_ucdiv 0000059f 0002(00000524:.text) SECTION=.text 0018 _COM_ucrem SECTION=.RLIB __COM_ucrem 000005b7 0002(00000343:.text) 0002(0000050a:.text) SECTION=.text 0019 _COM_uidiv SECTION=.RLIB __COM_uidiv 000005cc 0002(000003d3:.text) 0002(000003e7:.text) SECTION=.text 0020 rlink_generates_01 SECTION=.vect 0021 rlink_generates_02 SECTION=.security_id 0022 rlink_generates_03 SECTION= __s.vect 00000000 __s.const 00000080 __e.const 00000080 __s.constf 00000080 __e.constf 00000080 __s.sdata 00000080 __e.sdata 00000080 __e.vect 00000080 __s.data 00000082 __e.data 00000086 __s.option_byte 000000c0 __e.option_byte 000000c4 __s.security_id 000000c4 __s.text 000000ce __e.security_id 000000ce __e.text 00000582 __s.textf 00000582 __e.textf 00000582 __s.RLIB 00000582 __s.SLIB 00000582 __e.SLIB 00000582 __e.RLIB 000005e8 __s.bss 000ffce0 __RAM_ADDR_START 000ffce0 0003(00000548:.text) __e.bss 000ffceb __s.dataR 000ffcec __e.dataR 000ffcf0 __STACK_ADDR_END 000ffcfa __s.sbss 000ffe20 __STACK_ADDR_START 000ffe20 0003(00000542:.text) __e.sbss 000ffe27 __s.sdataR 000ffe28 __e.sdataR 000ffe28 __RAM_ADDR_END 000ffee0 0003(0000054b:.text)
.text 000000ce 00000581 4b4 1
.textf 00000582 00000582 0 1
.SLIB 00000582 00000582 0 1
.RLIB 00000582 000005e7 66 1
PROGRAM SECTION: 0000051a Byte(s)
Renesas Optimizing Linker (W2.04.00 ) 14-May-2017 07:31:34 *** Options *** -subcommand=DefaultBuild\EZPLforRL78v2andCCRLv102.clnk -Input=DefaultBuild\cstart.obj -Input=DefaultBuild\opt_byte.obj -Input=DefaultBuild\main.obj -Input=DefaultBuild\common.obj -Input=DefaultBuild\timer.obj -Input=DefaultBuild\int.obj -Input=DefaultBuild\port.obj -Input=DefaultBuild\watchdogtimer.obj -Input=DefaultBuild\system.obj -Input=DefaultBuild\systeminit.obj -Input=DefaultBuild\panel.obj -Input=DefaultBuild\digitalio.obj -Input=DefaultBuild\clk.obj -Input=DefaultBuild\74hc.obj -SECURITY_ID=00000000000000000000 -DEVICE=E:\tools\micom\Renesas\CS+\CC\Device\RL78\Devicefile\DR5F10Y47.DVF -DEBug -NOCOmpress -OUtput=DefaultBuild\EZPLforRL78v2andCCRLv102.abs -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4s.lib -LIBrary=E:\tools\micom\Renesas\CS+\CC\CC-RL\V1.02.00\lib\rl78nm4r.lib -ENTry=_start -LISt=DefaultBuild\EZPLforRL78v2andCCRLv102.map -SHow=ALL -AUTO_SECTION_LAYOUT -ROm=.data=.dataR -ROm=.sdata=.sdataR -NOMessage -NOLOgo -end *** Error information *** *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .textf 000000c4 000000c4 0 1 .SLIB 000000c4 000000c4 0 1 .text 000000ce 0000054e 481 1 .RLIB 00000583 000005e8 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 000004e7 Byte(s) *** Symbol List *** SECTION= FILE= START END SIZE SYMBOL ADDR SIZE INFO COUNTS OPT SECTION=.vect FILE=rlink_generates_01 00000000 0000007f 80 SECTION=.data FILE=DefaultBuild\main.obj 00000082 00000085 4 SECTION=.option_byte FILE=DefaultBuild\opt_byte.obj 000000c0 000000c3 4 SECTION=.security_id FILE=rlink_generates_02 000000c4 000000cd a SECTION=.text FILE=DefaultBuild\cstart.obj 000000ce 0000010f 42 _start 000000ce 0 entry,g 0 _exit 0000010e 0 none ,g 1 FILE=DefaultBuild\main.obj 00000110 0000054e 43f _main 00000110 6 func ,g 1 ch _main_loop 00000116 b func ,g 1 _hdwinit 00000121 a func ,g 2 _panel_init0 0000012b d func ,g 1 _panel 00000138 55 func ,g 1 _TM_10ms 0000018d 2e func ,g 1 _BitMemGet 000001bb 1d func ,g 3 _ByteMemGet 000001d8 8 func ,g 2 _BitMemSet 000001e0 3b func ,g 3 _ByteMemSet 0000021b 9 func ,g 4 _Port_Set 00000224 2c func ,g 1 _Port_Get 00000250 1d func ,g 1 _MD_INTTM00 0000026d 11 func ,g 0 _TM00_Init 0000027e 2f func ,g 1 _MD_INTP0 000002ad 2 func ,g 0 _MD_INTP1 000002af 2 func ,g 0 _MD_INTP2 000002b1 2 func ,g 0 _MD_INTP3 000002b3 2 func ,g 0 _MD_INTIT 000002b5 2 func ,g 0 _INT_Init 000002b7 2b func ,g 1 _PORT_Init 000002e2 1d func ,g 1 _SystemInit 000002ff f func ,g 1 _DGIN_Initialize 0000030e 12 func ,g 1 _DGIN_Counter 00000320 4 func ,g 2 _CLK_Initialize 00000324 13 func ,g 1 ch _IC74HC166_Initialize 00000337 12 func ,g 1 ch _DGIN_getValue 00000349 6a func ,g 1 ch _CLK_Evaluate 000003b3 8f func ,g 1 ch _CLK_Counter 00000442 4 func ,g 1 _IC_74HC166_Judge_State 00000446 42 func ,g 1 _IC_74HC166_Out_QH 00000488 77 func ,g 1 _IC74HC166_Counter 000004ff 4 func ,g 1 _DGOUT_setValue 00000503 24 func ,g 1 ch __CommonCode@0 00000527 a func ,l 2 __CommonCode@1 00000531 8 func ,l 2 ch __CommonCode@2 00000539 c func ,l 2 __CommonCode@3 00000545 a func ,l 2 SECTION=.RLIB FILE=memset 00000583 00000590 e _memset 00000583 0 none ,g 4 FILE=_COM_imul 00000591 0000059f f __COM_imul 00000591 0 none ,g 1 FILE=_COM_ucdiv 000005a0 000005b7 18 __COM_ucdiv 000005a0 0 none ,g 1 FILE=_COM_ucrem 000005b8 000005cc 15 __COM_ucrem 000005b8 0 none ,g 2 FILE=_COM_uidiv 000005cd 000005e8 1c __COM_uidiv 000005cd 0 none ,g 2 SECTION=.bss FILE=DefaultBuild\main.obj 000ffce0 000ffcea b _I_04 000ffce0 1 data ,g 2 _g_ucDGIN_LastRet 000ffce1 1 data ,g 2 _g_ucDGIN_ElapsedTime 000ffce2 1 data ,g 3 _g_ucDGIN_Count 000ffce3 1 data ,g 7 _g_ucCLK_LastOut@1 000ffce4 1 data ,l 3 _g_ushCLK_ElapsedTime@2 000ffce6 2 data ,l 3 _g_ucCLK_Count@3 000ffce8 1 data ,l 5 _g74HC166_LastCK 000ffce9 1 data ,g 3 _g74HC166_LastValue 000ffcea 1 data ,g 4 SECTION=.dataR FILE=DefaultBuild\main.obj 000ffcec 000ffcef 4 _F0303 000ffcec 1 data ,g 2 _F0512 000ffced 1 data ,g 0 _F0600 000ffcee 1 data ,g 2 _g74HC166_Count 000ffcef 1 data ,g 7 SECTION=.sbss FILE=DefaultBuild\main.obj 000ffe20 000ffe26 7 _fTm10ms 000ffe20 1 data ,g 3 _fTrg50ms 000ffe21 1 data ,g 2 _fTrg1s 000ffe22 1 data ,g 2 _fTrg10ms 000ffe23 1 data ,g 4 _SysTm10ms 000ffe24 1 data ,g 3 _SysTm50ms 000ffe25 1 data ,g 3 _SysTm1s 000ffe26 1 data ,g 3 Absolute value symbols FILE=rlink_generates_03 __s.text 000000ce 0 none ,g 0 __e.text 0000054f 0 none ,g 0 __s.textf 000000c4 0 none ,g 0 __e.textf 000000c4 0 none ,g 0 __s.const 00000080 0 none ,g 0 __e.const 00000080 0 none ,g 0 __s.constf 00000080 0 none ,g 0 __e.constf 00000080 0 none ,g 0 __s.data 00000082 0 none ,g 0 __e.data 00000086 0 none ,g 0 __s.sdata 00000080 0 none ,g 0 __e.sdata 00000080 0 none ,g 0 __s.bss 000ffce0 0 none ,g 0 __e.bss 000ffceb 0 none ,g 0 __s.sbss 000ffe20 0 none ,g 0 __e.sbss 000ffe27 0 none ,g 0 __s.dataR 000ffcec 0 none ,g 0 __e.dataR 000ffcf0 0 none ,g 0 __s.sdataR 000ffe28 0 none ,g 0 __e.sdataR 000ffe28 0 none ,g 0 __s.RLIB 00000583 0 none ,g 0 __e.RLIB 000005e9 0 none ,g 0 __s.SLIB 000000c4 0 none ,g 0 __e.SLIB 000000c4 0 none ,g 0 __s.option_byte 000000c0 0 none ,g 0 __e.option_byte 000000c4 0 none ,g 0 __s.vect 00000000 0 none ,g 0 __e.vect 00000080 0 none ,g 0 __s.security_id 000000c4 0 none ,g 0 __e.security_id 000000ce 0 none ,g 0 __RAM_ADDR_START 000ffce0 0 none ,g 1 __RAM_ADDR_END 000ffee0 0 none ,g 1 __STACK_ADDR_START 000ffe20 0 none ,g 1 __STACK_ADDR_END 000ffcfa 0 none ,g 0 *** Unfilled Areas *** AREA START END *** Delete Symbols *** SYMBOL SIZE INFO _WDT_Reset 4 func ,g _MOV1_ 1 func ,g _NOT1_ 7 func ,g _WAIT d func ,g _WDT_Init 1 func ,g _Clock_Init 1 func ,g _DGIN_Counter_Clear 4 func ,g _CLK_Counter_Clear 4 func ,g _IC74HC166_Counter_Clear 4 func ,g _fTx0Done 1 data ,g _fTx6Done 1 data ,g _F0500 1 data ,g _F0501 1 data ,g _F0502 1 data ,g _F0505 1 data ,g _F0506 1 data ,g _F0507 1 data ,g _F0508 1 data ,g _F0509 1 data ,g _F0510 1 data ,g _F0511 1 data ,g *** Variable Vector Table List *** ADDRESS SYMBOL/ADDRESS 00 _start 02 04 06 _MD_INTP0 08 _MD_INTP1 0a 0c 0e 10 12 _MD_INTTM00 14 16 18 1a _MD_INTP2 1c _MD_INTP3 1e 20 22 24 26 _MD_INTIT 28 2a 2c 2e 30 32 34 36 38 3a 3c 3e 40 42 44 46 48 4a 4c 4e 50 52 54 56 58 5a 5c 5e 60 62 64 66 68 6a 6c 6e 70 72 74 76 78 7a 7c 7e *** Cross Reference List *** No Unit Name Global.Symbol Location External Infomation ---- ----------- --------------- -------- --------------------- 0001 cstart SECTION=.text _start 000000ce _exit 0000010e 0001(0000010f:.text) SECTION=.textf SECTION=.const SECTION=.constf SECTION=.data SECTION=.sdata SECTION=.bss SECTION=.sbss SECTION=.dataR SECTION=.sdataR SECTION=.RLIB SECTION=.SLIB SECTION=.dataR SECTION=.sdataR 0002 opt_byte SECTION=.option_byte 0003 main SECTION=.sbss _fTm10ms 000ffe20 0003(00000194:.text) 0003(000001b6:.text) 0003(0000027a:.text) _fTrg50ms 000ffe21 0003(00000190:.text) 0003(000001a7:.text) _fTrg1s 000ffe22 0003(00000192:.text) 0003(000001b4:.text) _fTrg10ms 000ffe23 0003(00000142:.text) 0003(00000152:.text) 0003(0000018e:.text) 0003(00000199:.text) _SysTm10ms 000ffe24 0003(00000270:.text) 0003(00000272:.text) 0003(00000278:.text) _SysTm50ms 000ffe25 0003(0000019d:.text) 0003(0000019f:.text) 0003(000001a5:.text) _SysTm1s 000ffe26 0003(000001aa:.text) 0003(000001ac:.text) 0003(000001b2:.text) SECTION=.text _main 00000110 0001(0000010b:.text) _main_loop 00000116 _hdwinit 00000121 0001(000000d3:.text) 0003(00000111:.text) _panel_init0 0000012b 0003(00000114:.text) _panel 00000138 0003(00000117:.text) _TM_10ms 0000018d 0003(0000011d:.text) _BitMemGet 000001bb 0003(00000373:.text) 0003(000003bf:.text) 0003(00000465:.text) _ByteMemGet 000001d8 0003(0000037e:.text) 0003(0000054c:.text) _BitMemSet 000001e0 0003(0000042f:.text) 0003(00000481:.text) 0003(0000052e:.text) _ByteMemSet 0000021b 0003(0000031e:.text) 0003(000003ac:.text) 0003(000004ac:.text) 0003(00000542:.text) _Port_Set 00000224 0003(00000525:.text) _Port_Get 00000250 0003(0000035e:.text) _MD_INTTM00 0000026d _TM00_Init 0000027e 0003(0000030c:.text) _MD_INTP0 000002ad _MD_INTP1 000002af _MD_INTP2 000002b1 _MD_INTP3 000002b3 _MD_INTIT 000002b5 _INT_Init 000002b7 0003(00000309:.text) _PORT_Init 000002e2 0003(00000306:.text) _SystemInit 000002ff 0003(00000125:.text) _DGIN_Initialize 0000030e 0003(0000012d:.text) _DGIN_Counter 00000320 0003(00000130:.text) 0003(0000014f:.text) _CLK_Initialize 00000324 0003(00000133:.text) _IC74HC166_Initialize 00000337 0003(00000136:.text) _DGIN_getValue 00000349 0003(00000147:.text) _CLK_Evaluate 000003b3 0003(00000159:.text) _CLK_Counter 00000442 0003(00000161:.text) _IC_74HC166_Judge_State 00000446 0003(0000016a:.text) _IC_74HC166_Out_QH 00000488 0003(0000017b:.text) _IC74HC166_Counter 000004ff 0003(00000183:.text) _DGOUT_setValue 00000503 0003(0000018b:.text) SECTION=.bss _I_04 000ffce0 0003(0000014c:.text) 0003(00000173:.text) _g_ucDGIN_LastRet 000ffce1 0003(00000370:.text) 0003(0000052b:.text) _g_ucDGIN_ElapsedTime 000ffce2 0003(0000031b:.text) 0003(0000037b:.text) 0003(000003a9:.text) _g_ucDGIN_Count 000ffce3 0003(00000139:.text) 0003(00000317:.text) 0003(00000321:.text) 0003(0000036d:.text) 0003(00000378:.text) 0003(000003a6:.text) 0003(00000528:.text) _g74HC166_LastCK 000ffce9 0003(0000033b:.text) 0003(00000462:.text) 0003(0000047e:.text) _g74HC166_LastValue 000ffcea 0003(00000344:.text) 0003(000004a9:.text) 0003(0000053f:.text) 0003(00000549:.text) SECTION=.dataR _F0303 000ffcec 0003(0000015e:.text) 0003(00000164:.text) _F0512 000ffced _F0600 000ffcee 0003(00000180:.text) 0003(00000186:.text) _g74HC166_Count 000ffcef 0003(0000013f:.text) 0003(0000045f:.text) 0003(0000047b:.text) 0003(000004a5:.text) 0003(00000500:.text) 0003(0000053c:.text) 0003(00000546:.text) SECTION=.data 0004 common 0005 timer 0006 int 0007 port 0008 watchdogtimer 0009 system 0010 systeminit 0011 panel 0012 digitalio 0013 clk 0014 74hc 0015 memset SECTION=.RLIB _memset 00000583 0003(0000032b:.text) 0003(00000335:.text) 0003(0000033e:.text) 0003(00000347:.text) SECTION=.text 0016 _COM_imul SECTION=.RLIB __COM_imul 00000591 0003(000003dc:.text) SECTION=.text 0017 _COM_ucdiv SECTION=.RLIB __COM_ucdiv 000005a0 0003(00000534:.text) SECTION=.text 0018 _COM_ucrem SECTION=.RLIB __COM_ucrem 000005b8 0003(00000358:.text) 0003(0000051b:.text) SECTION=.text 0019 _COM_uidiv SECTION=.RLIB __COM_uidiv 000005cd 0003(000003e6:.text) 0003(000003f9:.text) SECTION=.text 0020 rlink_generates_01 SECTION=.vect 0021 rlink_generates_02 SECTION=.security_id 0022 rlink_generates_03 SECTION= __s.vect 00000000 __s.const 00000080 __e.const 00000080 __s.constf 00000080 __e.constf 00000080 __s.sdata 00000080 __e.sdata 00000080 __e.vect 00000080 __s.data 00000082 __e.data 00000086 __s.option_byte 000000c0 __s.textf 000000c4 __e.textf 000000c4 __s.SLIB 000000c4 __e.SLIB 000000c4 __e.option_byte 000000c4 __s.security_id 000000c4 __s.text 000000ce __e.security_id 000000ce __e.text 0000054f __s.RLIB 00000583 __e.RLIB 000005e9 __s.bss 000ffce0 __RAM_ADDR_START 000ffce0 0001(000000d6:.text) __e.bss 000ffceb __s.dataR 000ffcec __e.dataR 000ffcf0 __STACK_ADDR_END 000ffcfa __s.sbss 000ffe20 __STACK_ADDR_START 000ffe20 0001(000000d0:.text) __e.sbss 000ffe27 __s.sdataR 000ffe28 __e.sdataR 000ffe28 __RAM_ADDR_END 000ffee0 0001(000000d9:.text)
.textf 000000c4 000000c4 0 1
.SLIB 000000c4 000000c4 0 1
.RLIB 00000583 000005e8 66 1
CC-RL V1.04.00 で確認しましたが、V1.02 と比べてコード生成の結果が一部変わり .text セクションのサイズが少々し増大している以外、リンクの結果は凡そ同じものとなりました。
(1) 機能するパターン
Renesas Optimizing Linker (W2.06.00 ) 16-May-2017 22:34:21 ... *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .text 000000ce 00000570 4a3 1 .textf 00000571 00000571 0 1 .SLIB 00000571 00000571 0 1 .RLIB 00000571 000005d6 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 00000509 Byte(s) ... *** Delete Symbols *** SYMBOL SIZE INFO _WDT_Reset 4 func ,g _MOV1_ 1 func ,g _NOT1_ 7 func ,g _WAIT d func ,g _WDT_Init 1 func ,g _Clock_Init 1 func ,g _DGIN_Counter_Clear 4 func ,g _CLK_Counter_Clear 4 func ,g _IC74HC166_Counter_Clear 4 func ,g _fTx0Done 1 data ,g _fTx6Done 1 data ,g 以後省略 ...
(2) 機能しないパターンその1
Renesas Optimizing Linker (W2.06.00 ) 16-May-2017 22:34:59 ... *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .text 000000ce 000005a3 4d6 1 .textf 000005a4 000005a4 0 1 .SLIB 000005a4 000005a4 0 1 .RLIB 000005a4 00000609 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 0000053c Byte(s) ... *** Delete Symbols *** SYMBOL SIZE INFO _fTx0Done 1 data ,g _fTx6Done 1 data ,g 以後省略 ...
(3) 機能しないパターンその2
Renesas Optimizing Linker (W2.06.00 ) 16-May-2017 22:27:01 ... *** Mapping List *** SECTION START END SIZE ALIGN .vect 00000000 0000007f 80 0 .const 00000080 00000080 0 2 .constf 00000080 00000080 0 2 .sdata 00000080 00000080 0 2 .data 00000082 00000085 4 2 .option_byte 000000c0 000000c3 4 1 .security_id 000000c4 000000cd a 1 .textf 000000c4 000000c4 0 1 .SLIB 000000c4 000000c4 0 1 .text 000000ce 00000570 4a3 1 .RLIB 000005a5 0000060a 66 1 .bss 000ffce0 000ffcea b 2 .dataR 000ffcec 000ffcef 4 2 .sbss 000ffe20 000ffe26 7 2 .sdataR 000ffe28 000ffe28 0 2 *** Total Section Size *** RAMDATA SECTION: 00000016 Byte(s) ROMDATA SECTION: 00000092 Byte(s) PROGRAM SECTION: 00000509 Byte(s) ... *** Delete Symbols *** SYMBOL SIZE INFO _WDT_Reset 4 func ,g _MOV1_ 1 func ,g _NOT1_ 7 func ,g _WAIT d func ,g _WDT_Init 1 func ,g _Clock_Init 1 func ,g _DGIN_Counter_Clear 4 func ,g _CLK_Counter_Clear 4 func ,g _IC74HC166_Counter_Clear 4 func ,g _fTx0Done 1 data ,g _fTx6Done 1 data ,g 以後省略 ...
fujitaさん、こんにちは、NoMaYです。かなり時間が経ってしまっていて申し訳ありませんが、CC-RL V1.04で確認して頂きまして、どうもすみませんでした。それで、knight2000lite2のcstart.asmですが、試してみると以下の画面コピーのように期待通りには動きませんでした。調べてみると、ROMコピールーチンでROMから読み出す時にESプレフィクス(ES=0にした上での)が付いていませんでした。或いは、0xF8○○○のミラー領域からの読み出しになるようにアドレスに0x8000だけ下駄を履かせて読み出すようにするか、どちらかの必要があると思います。CC-RLで以下のような記述が出来るとすっきりするのですが、どうも出来ないようです。(出来たとして、ここでしか出番が無さそうな記法ですが、、、)例えば MOVW HL,#LOWW(STARTOF(.data) + 0x8000)や MOVW HL,#LOWW(STARTOF(.sdata) + 0x8000)とか MOVW HL,#MIRLW(STARTOF(.data))や MOVW HL,#MIRLW(STARTOF(.sdata))とか、、、プロジェクトのファイル一式CCRLv102andCStartG10Fujita.NG.zip画面コピー[追記]あっ、すみません、、、誤) /* sdatavar ==> 0x5648 --> 正常 */正) /* sdatavar ==> 0x5678 --> 正常 */さらに、今更ながら、かつ、我ながら、何を考えていたのか思い出せないのですが、どうしてhdwinit()とmain()の2箇所に分けて違うもの(bssの変数とdataの変数)を別々にチェックしたのだろうか、と思わずにはいられません。hdwinit()かmain()の片方だけでbssの変数とdataの変数の両方をチェックすれば良かったのに、と今は思います、、、
宜しければ以下の添付の cstart.asm をお試し下さい。
cstart.asm.zip